8000 deps: V8: cherry-pick 13192d6e10fa by luyahan · Pull Request #50648 · nodejs/node · GitHub
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deps: V8: cherry-pick 13192d6e10fa #50648

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deps: V8: cherry-pick 13192d6e10fa 
Original commit message:

    [riscv][tagged-ptr] Convert more Objects to Tagged<>

    Port commit 064b9a7903b793734b6c03a86ee53a2dc85f0f80

    Bug: v8:12710

    Change-Id: If076ca5cd9e9d175c20fc3611e03d39c0260404d
    Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4837830
    Reviewed-by: Ji Qiu <qiuji@iscas.ac.cn>
    Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn>
    Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
    Cr-Commit-Position: refs/heads/main@{#89780}

Refs: v8/v8@13192d6
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@luyahan
luyahan committed Nov 10, 2023
commit b22d500decc1980f910de210b1512604e5a793ab
2 changes: 1 addition & 1 deletion common.gypi
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Expand Up @@ -36,7 +36,7 @@

# Reset this number to 0 on major V8 upgrades.
# Increment by one for each non-official patch applied to deps/v8.
'v8_embedder_string': '-node.14',
'v8_embedder_string': '-node.15',

##### V8 defaults for Node.js #####

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2 changes: 1 addition & 1 deletion deps/v8/src/builtins/riscv/builtins-riscv.cc
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Expand Up @@ -1673,7 +1673,7 @@ static void Generate_InterpreterEnterBytecode(MacroAssembler* masm) {
// Set the return address to the correct point in the interpreter entry
// trampoline.
Label builtin_trampoline, trampoline_loaded;
Smi interpreter_entry_return_pc_offset(
Tagged<Smi> interpreter_entry_return_pc_offset(
masm->isolate()->heap()->interpreter_entry_return_pc_offset());
DCHECK_NE(interpreter_entry_return_pc_offset, Smi::zero());

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15 changes: 8 additions & 7 deletions deps/v8/src/codegen/riscv/assembler-riscv-inl.h
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Expand Up @@ -128,9 +128,9 @@ Handle<HeapObject> Assembler::compressed_embedded_object_handle_at(
}

void Assembler::deserialization_set_special_target_at(
Address instruction_payload, Code code, Address target) {
Address instruction_payload, Tagged<Code> code, Address target) {
set_target_address_at(instruction_payload,
!code.is_null() ? code.constant_pool() : kNullAddress,
!code.is_null() ? code->constant_pool() : kNullAddress,
target);
}

Expand Down Expand Up @@ -159,12 +159,13 @@ void Assembler::deserialization_set_target_internal_reference_at(
}
}

HeapObject RelocInfo::target_object(PtrComprCageBase cage_base) {
Tagged<HeapObject> RelocInfo::target_object(PtrComprCageBase cage_base) {
DCHECK(IsCodeTarget(rmode_) || IsEmbeddedObjectMode(rmode_));
if (IsCompressedEmbeddedObject(rmode_)) {
return HeapObject::cast(Object(V8HeapCompressionScheme::DecompressTagged(
cage_base,
Assembler::target_compressed_address_at(pc_, constant_pool_))));
return HeapObject::cast(
Tagged<Object>(V8HeapCompressionScheme::DecompressTagged(
cage_base,
Assembler::target_compressed_address_at(pc_, constant_pool_))));
} else {
return HeapObject::cast(
Object(Assembler::target_address_at(pc_, constant_pool_)));
Expand All @@ -186,7 +187,7 @@ Handle<HeapObject> RelocInfo::target_object_handle(Assembler* origin) {
}
}

void RelocInfo::set_target_object(HeapObject target,
void RelocInfo::set_target_object(Tagged<HeapObject> target,
ICacheFlushMode icache_flush_mode) {
DCHECK(IsCodeTarget(rmode_) || IsEmbeddedObjectMode(rmode_));
if (IsCompressedEmbeddedObject(rmode_)) {
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2 changes: 1 addition & 1 deletion deps/v8/src/codegen/riscv/assembler-riscv.h
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Expand Up @@ -288,7 +288,7 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase,
// This is for calls and branches within generated code. The serializer
// has already deserialized the lui/ori instructions etc.
inline static void deserialization_set_special_target_at(Address location,
Code code,
Tagged<Code> code,
Address target);

// Get the size of the special target encoded at 'instruction_payload'.
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8 changes: 4 additions & 4 deletions deps/v8/src/execution/riscv/simulator-riscv.cc
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Expand Up @@ -1889,7 +1889,7 @@ void RiscvDebugger::Debug() {
sreg_t value;
StdoutStream os;
if (GetValue(arg1, &value)) {
Object obj(value);
Tagged<Object> obj(value);
os << arg1 << ": \n";
#ifdef DEBUG
Print(obj, os);
Expand Down Expand Up @@ -1938,7 +1938,7 @@ void RiscvDebugger::Debug() {
PrintF(" 0x%012" PRIxPTR " : 0x%016" REGIx_FORMAT
" %14" REGId_FORMAT " ",
reinterpret_cast<intptr_t>(cur), *cur, *cur);
Object obj(*cur);
Tagged<Object> obj(*cur);
Heap* current_heap = sim_->isolate_->heap();
if (IsSmi(obj) ||
IsValidHeapObject(current_heap, HeapObject::cast(obj))) {
Expand Down Expand Up @@ -4815,7 +4815,7 @@ bool Simulator::DecodeRvvVS() {
Builtin Simulator::LookUp(Address pc) {
for (Builtin builtin = Builtins::kFirst; builtin <= Builtins::kLast;
++builtin) {
if (builtins_.code(builtin).contains(isolate_, pc)) return builtin;
if (builtins_.code(builtin)->contains(isolate_, pc)) return builtin;
}
return Builtin::kNoBuiltinId;
}
Expand All @@ -4832,7 +4832,7 @@ void Simulator::DecodeRVIType() {
if (builtin != Builtin::kNoBuiltinId) {
auto code = builtins_.code(builtin);
if ((rs1_reg() != ra || imm12() != 0)) {
if ((Address)get_pc() == code.instruction_start()) {
if ((Address)get_pc() == code->instruction_start()) {
sreg_t arg0 = get_register(a0);
sreg_t arg1 = get_register(a1);
sreg_t arg2 = get_register(a2);
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2 changes: 1 addition & 1 deletion deps/v8/src/regexp/riscv/regexp-macro-assembler-riscv.cc
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Expand Up @@ -1216,7 +1216,7 @@ static T* frame_entry_address(Address re_frame, int frame_offset) {
int64_t RegExpMacroAssemblerRISCV::CheckStackGuardState(Address* return_address,
Address raw_code,
Address re_frame) {
InstructionStream re_code = InstructionStream::cast(Object(raw_code));
Tagged<InstructionStream> re_code = InstructionStream::cast(Object(raw_code));
return NativeRegExpMacroAssembler::CheckStackGuardState(
frame_entry<Isolate*>(re_frame, kIsolateOffset),
static_cast<int>(frame_entry<int64_t>(re_frame, kStartIndexOffset)),
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