macros_mimxrt
This documentation is part of the MicroPython project, http://micropython.org/
These MIMXRT_* macros have been scanned from the source code in the MicroPython repository. The descriptions for each macro have been generated based on the surrounding code context using the OpenAI o3-mini model.
This collection of macros configures the pin assignments and settings for the SEMC (Static External Memory Controller) interface on the MIMXRT1170 evaluation board. It specifies the configurations for various address, data, and control signals, enabling proper communication with external memory devices.
| Macro | Description | Sample value(s) |
|---|---|---|
MIMXRT_IOMUXC_SEMC_ADDR00 |
Defines the pin configuration for SEMC address line 0 on the MIMXRT1170 EVK. | IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 |
MIMXRT_IOMUXC_SEMC_ADDR01 |
Defines the pin configuration for SEMC address line 01 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 |
MIMXRT_IOMUXC_SEMC_ADDR02 |
Defines the pin configuration for SEMC address line 2 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 |
MIMXRT_IOMUXC_SEMC_ADDR03 |
Defines the pin configuration for SEMC address line 3 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 |
MIMXRT_IOMUXC_SEMC_ADDR04 |
Defines the pin configuration for SEMC address line 04 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 |
MIMXRT_IOMUXC_SEMC_ADDR05 |
Defines the pin configuration for SEMC address line 5 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 |
MIMXRT_IOMUXC_SEMC_ADDR06 |
Pin configuration for SEMC address line 06 on MIMXRT boards. | IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 |
MIMXRT_IOMUXC_SEMC_ADDR07 |
Pin configuration for SEMC address line 07 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 |
MIMXRT_IOMUXC_SEMC_ADDR08 |
Defines the pin configuration for SEMC address line 08 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 |
MIMXRT_IOMUXC_SEMC_ADDR09 |
Pin configuration for SEMC address line 09 on MIMXRT boards. | IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 |
MIMXRT_IOMUXC_SEMC_ADDR10 |
Defines the pin configuration for SEMC address line 10 on the MIMXRT1170 EVK. | IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 |
MIMXRT_IOMUXC_SEMC_ADDR11 |
Defines the pin configuration for SEMC address line 11 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 |
MIMXRT_IOMUXC_SEMC_ADDR12 |
Pin configuration for SEMC address line 12 on MIMXRT boards. | IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 |
MIMXRT_IOMUXC_SEMC_BA0 |
Defines the pin configuration for SEMC Bank Address 0. | IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 |
MIMXRT_IOMUXC_SEMC_BA1 |
Pin configuration for SEMC Bank Address 1 on the MIMXRT1170 EVK. | IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 |
MIMXRT_IOMUXC_SEMC_CAS |
Defines the pin configuration for the SEMC CAS signal on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_24_SEMC_CAS |
MIMXRT_IOMUXC_SEMC_CKE |
Defines the pin configuration for the SEMC CKE signal on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_27_SEMC_CKE |
MIMXRT_IOMUXC_SEMC_CLK |
Defines the pin configuration for the SEMC clock signal. | IOMUXC_GPIO_EMC_B1_26_SEMC_CLK |
MIMXRT_IOMUXC_SEMC_CS0 |
Defines the pin configuration for SEMC Chip Select 0. | IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 |
MIMXRT_IOMUXC_SEMC_DATA00 |
Pin configuration for SEMC data line 0 on MIMXRT boards. | IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 |
MIMXRT_IOMUXC_SEMC_DATA01 |
Defines the pin mapping for SEMC data line 1 to the IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01. | IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 |
MIMXRT_IOMUXC_SEMC_DATA02 |
Defines the pin mapping for SEMC data line 2 to IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02. | IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 |
MIMXRT_IOMUXC_SEMC_DATA03 |
Defines the pin configuration for SEMC_DATA03 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 |
MIMXRT_IOMUXC_SEMC_DATA04 |
Defines the pin configuration for SEMC_DATA04 on the MIMXRT1170 platform. | IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 |
MIMXRT_IOMUXC_SEMC_DATA05 |
Pin configuration for SEMC_DATA05 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 |
MIMXRT_IOMUXC_SEMC_DATA06 |
Pin configuration for SEMC_DATA06 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 |
MIMXRT_IOMUXC_SEMC_DATA07 |
Defines the pin configuration for SEMC_DATA07 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 |
MIMXRT_IOMUXC_SEMC_DATA08 |
Pin configuration for SEMC_DATA08 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 |
MIMXRT_IOMUXC_SEMC_DATA09 |
Pin configuration for SEMC_DATA09 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 |
MIMXRT_IOMUXC_SEMC_DATA10 |
Pin configuration for SEMC_DATA10 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 |
MIMXRT_IOMUXC_SEMC_DATA11 |
Pin configuration for SEMC_DATA11 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 |
MIMXRT_IOMUXC_SEMC_DATA12 |
Defines the pin configuration for SEMC_DATA12 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 |
MIMXRT_IOMUXC_SEMC_DATA13 |
Pin configuration for SEMC_DATA13 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 |
MIMXRT_IOMUXC_SEMC_DATA14 |
Defines the pin configuration for SEMC_DATA14 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 |
MIMXRT_IOMUXC_SEMC_DATA15 |
Pin configuration for SEMC_DATA15 on the MIMXRT1170 EVK board. | IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 |
MIMXRT_IOMUXC_SEMC_DATA16 |
Pin configuration for SEMC_DATA16 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 |
MIMXRT_IOMUXC_SEMC_DATA17 |
Pin configuration for SEMC_DATA17 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 |
MIMXRT_IOMUXC_SEMC_DATA18 |
Pin configuration for SEMC_DATA18 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 |
MIMXRT_IOMUXC_SEMC_DATA19 |
Pin configuration for SEMC_DATA19 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 |
MIMXRT_IOMUXC_SEMC_DATA20 |
Defines the pin configuration for SEMC_DATA20 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 |
MIMXRT_IOMUXC_SEMC_DATA21 |
Pin configuration for SEMC_DATA21 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 |
MIMXRT_IOMUXC_SEMC_DATA22 |
Pin configuration for SEMC_DATA22 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 |
MIMXRT_IOMUXC_SEMC_DATA23 |
Pin configuration for SEMC_DATA23 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 |
MIMXRT_IOMUXC_SEMC_DATA24 |
Pin configuration for SEMC_DATA24 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 |
MIMXRT_IOMUXC_SEMC_DATA25 |
Pin configuration for SEMC_DATA25 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 |
MIMXRT_IOMUXC_SEMC_DATA26 |
Pin configuration for SEMC_DATA26 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 |
MIMXRT_IOMUXC_SEMC_DATA27 |
Pin configuration for SEMC_DATA27 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 |
MIMXRT_IOMUXC_SEMC_DATA28 |
Defines the pin configuration for SEMC_DATA28 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 |
MIMXRT_IOMUXC_SEMC_DATA29 |
Pin configuration for SEMC_DATA29 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 |
MIMXRT_IOMUXC_SEMC_DATA30 |
Pin configuration for SEMC_DATA30 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 |
MIMXRT_IOMUXC_SEMC_DATA31 |
Pin configuration for SEMC_DATA31 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 |
MIMXRT_IOMUXC_SEMC_DM00 |
Pin configuration for SEMC data mask signal DM00 on GPIO EMC B1_08. | IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 |
MIMXRT_IOMUXC_SEMC_DM01 |
Defines the pin configuration for SEMC data mask signal DM01. | IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 |
MIMXRT_IOMUXC_SEMC_DM02 |
Pin configuration for SEMC_DM02 on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 |
MIMXRT_IOMUXC_SEMC_DM03 |
Pin configuration for SEMC data mask signal DM03 on the MIMXRT1170. | IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 |
MIMXRT_IOMUXC_SEMC_DQS |
Defines the pin configuration for the SEMC DQS signal on the MIMXRT1170 board. | IOMUXC_GPIO_EMC_B1_39_SEMC_DQS |
MIMXRT_IOMUXC_SEMC_DQS4 |
Defines the IOMUXC configuration for SEMC DQS4 signal on GPIO pin. | IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 |
MIMXRT_IOMUXC_SEMC_RAS |
Defines the pin configuration for the SEMC RAS signal on the MIMXRT series. | IOMUXC_GPIO_EMC_B1_25_SEMC_RAS |
MIMXRT_IOMUXC_SEMC_WE |
Pin configuration for the SEMC write enable signal. | IOMUXC_GPIO_EMC_B1_28_SEMC_WE |