8000 ethernet support for NUCLEO_F746ZG by cfpena · Pull Request #5085 · micropython/micropython · GitHub
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ethernet support for NUCLEO_F746ZG #5085

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ethernet support for NUCLEO_F746ZG #5085

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0ed8d47
ethernet support for NUCLEO_F746ZG
Sep 6, 2019
215699a
ssl enable for ethernet
Sep 10, 2019
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16 changes: 14 additions & 2 deletions ports/stm32/boards/NUCLEO_F746ZG/mpconfigboard.h
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@

#define MICROPY_HW_BOARD_NAME "NUCLEO-F746ZG"
#define MICROPY_HW_MCU_NAME "STM32F746"

#define MICROPY_HW_HAS_SWITCH (1)
#define MICROPY_HW_HAS_FLASH (1)
#define MICROPY_HW_ENABLE_RNG (1)
Expand All @@ -26,7 +26,7 @@
// 151-180 MHz => 5 wait states
// 181-210 MHz => 6 wait states
// 211-216 MHz => 7 wait states
#define MICROPY_HW_FLASH_LATENCY FLASH_LATENCY_7 // 210-216 MHz needs 7 wait states
#define MICROPY_HW_FLASH_LATENCY (FLASH_LATENCY_7) // 210-216 MHz needs 7 wait states

// UART config
< 10000 /td> #define MICROPY_HW_UART2_TX (pin_D5)
Expand Down Expand Up @@ -75,3 +75,15 @@
#define MICROPY_HW_USB_FS (1)
#define MICROPY_HW_USB_VBUS_DETECT_PIN (pin_A9)
#define MICROPY_HW_USB_OTG_ID_PIN (pin_A10)


// Ethernet via RMII
#define MICROPY_HW_ETH_MDC (pin_C1)
#define MICROPY_HW_ETH_MDIO (pin_A2)
#define MICROPY_HW_ETH_RMII_REF_CLK (pin_A1)
#define MICROPY_HW_ETH_RMII_CRS_DV (pin_A7)
#define MICROPY_HW_ETH_RMII_RXD0 (pin_C4)
#define MICROPY_HW_ETH_RMII_RXD1 (pin_C5)
#define MICROPY_HW_ETH_RMII_TX_EN (pin_G11)
#define MICROPY_HW_ETH_RMII_TXD0 (pin_G13)
#define MICROPY_HW_ETH_RMII_TXD1 (pin_B13)
5 changes: 5 additions & 0 deletions ports/stm32/boards/NUCLEO_F746ZG/mpconfigboard.mk
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Expand Up @@ -4,3 +4,8 @@ AF_FILE = boards/stm32f746_af.csv
LD_FILES = boards/stm32f746.ld boards/common_ifs.ld
TEXT0_ADDR = 0x08000000
TEXT1_ADDR = 0x08020000

# MicroPython settings
MICROPY_PY_LWIP = 1
MICROPY_PY_USSL = 1
MICROPY_SSL_MBEDTLS = 1
9 changes: 9 additions & 0 deletions ports/stm32/boards/NUCLEO_F746ZG/pins.csv
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Expand Up @@ -66,3 +66,12 @@ UART6_RX,PG9
SPI_B_NSS,PA4
SPI_B_SCK,PB3
SPI_B_MOSI,PB5
ETH_MDC,PC1
ETH_MDIO,PA2
ETH_RMII_REF_CLK,PA1
ETH_RMII_CRS_DV,PA7
ETH_RMII_RXD0,PC4
ETH_RMII_RXD1,PC5
ETH_RMII_TX_EN,PG11
ETH_RMII_TXD0,PG13
ETH_RMII_TXD1,PB13
0