RISC-V Single Cycle RV32I core

This is a Single Cycle processor running the RV32I implementation, hence a 32-bits cpu, written in SystemVerilog. It was made for learning purpouses, it's not intended for production.

Thanks to

@BrunoLevy and his amazing tutorial From Blinker to RiscV.

Although that design is very different from the one made in this repo (that tutorial uses a monolithic approach to build the RiscV cpu, whereas I use modular approach), I reused a lot of concepts and code from that tutorial, including the Memory mapped devices idea and the GNU toolchain makefiles.

RISC-V reference

I recommend 100% to read the RISC-V Reference Manual, maybe not complete but those sections mentioning the RV32I implementation.

Architecture

The architecture was heavily inspired in the 32-bits Single Cycle MIPS processor explained in Digital Design and Computer Architecture book. Note that instruction and data are stored in separate memories.

FPGA Board

Any board should be compatible that has enough LUT's. This is running on the Digilent Basys 3 board and uses a little bit less than 1,000 LUT's without considering the slow clock circuit.

Top module and RiscV module

The top module is RiscVTop.sv, which includes the wiring to the slow clock, the 7-segments displays and some leds. The cpu itself is the RiscV.sv module which also includes the Instruction Memory and the Data Memory.

Programming using the GNU Toolchain

I documented the steps in this repository.