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@SethGower
Seth Gower SethGower
I am an FPGA Engineer with experience designing digital systems for SDR applications. I currently work at Mastodon Design.

Mastodon Design Rochester, NY

@teburd
Tom Burdick teburd
Duct tape is the best tape.

Intel Chicago, IL

@easygoal
Guoyou easygoal
Digital Design engineer works on Linux

Shanghai, China

@matzesc
Mathias Schmalisch matzesc
FPGA Design, Digital Signal Processing, Wireless Communications, Cryptography, Embedded Systems, Linux, Windows, Emacs

Virginia, USA

@lukipedio
Luca Colombini lukipedio
Senior design engineer @ CAEN

CAEN S.p.A. Italy

@Ahmad-Zaklouta
Ahmad Zaklouta Ahmad-Zaklouta
Interested in FPGA, VHDL, C programming, and ARM

Synective Labs Stockholm

@gurpreetshanky
gurpreetshanky
Deep Learning Engineer

Magna Detroit

@umarcor
Unai Martinez-Corral umarcor

UPV/EHU Bilbo, Bizkaia, Euskadi, Spain, Europe

@jevinskie
Jevin Sweval jevinskie
Senior Security Researcher, compilers/optimizations/[de]obfuscation, SCA, program analysis, NFC ninja, HW hacker w/ FPGA hammer Previously Apple Pay Security

Lafayette, Indiana

@kammoh
Kamyar Mohajerani kammoh
PhD student at George Mason University and member of Cryptographic Engineering Research Group

@GMUCERG Fairfax, VA

@benreynwar
Ben Reynwar benreynwar
Interested in the intersection of hardware design, formal methods and machine learning.

USC, Information Sciences Institiute Tucson, Arizona, USA

@mariuselv
mariuselv mariuselv
VHDL, Python, UVVM

Bitvis / Inventas Norway

@Paebbels
Patrick Lehmann Paebbels
Vice-Chair of the IEEE P1076 Working Group (VHDL Analysis and Standardization Group- VASG). I'm a VHDL expert and FPGA-technology trainer at @PLC2.

@PLC2 Bötzingen, Germany

@shravan-shandilya
Shravan Shandilya shravan-shandilya
A generalist who can become a specialist in logarithmic time

Bangalore