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ShanghaiTech University
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Elongate technology demonstrator for zcu102 board using the binarized neural network
Zynq Dynamic Energy Managemen (Zynq-DEM)
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。
Verilog AXI components for FPGA implementation
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations
This is a JPEG encoder using SJPEG and Vivado HLS to accelerate certain blocks
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
Unofficial implementation of LSQ-Net, a neural network quantization framework
A PyTorch implementation of MobileNet V2 architecture and pretrained model.
Conditional channel- and precision-pruning on neural networks
PyTorch implementation of Data Free Quantization Through Weight Equalization and Bias Correction.
micronet, a model compression and deploy lib. compression: 1、quantization: quantization-aware-training(QAT), High-Bit(>2b)(DoReFa/Quantization and Training of Neural Networks for Efficient Integer-…
XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.
Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated
GPU & Accelerator process monitoring for AMD, Apple, Huawei, Intel, NVIDIA and Qualcomm
Install and Run petalinux-v2018.2 by docker