10BC0 Pull requests · iree-org/iree · GitHub
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Pull requests list

[Codegen] Drop Descriptor flag uses on hal.binding.subspan and use MemoryAccessBitfield to represent tensor dispatch access
#22236 opened Oct 7, 2025 by RiverDave • Draft
Integrate llvm/llvm-project@7546bd3
#22234 opened Oct 7, 2025 by newling • Draft
Add mmt4d ukernel for riscv64's zvfhmin and zvfh feature, for types f16xf16->f16/f32
#22231 opened Oct 7, 2025 by adeel10x Loading…
7
[Do not review] Test HF token in IREE CI
#22228 opened Oct 7, 2025 by pravg-amd • Draft
[python] Set up binding for preprocessing transform ops
#22227 opened Oct 7, 2025 by bangtianliu Loading…
4
Improving ElideAsyncCopiesPass to subsume ElideAsyncTransfersPass. compiler/dialects Relating to the IREE compiler dialects (flow, hal, vm)
#22226 opened Oct 6, 2025 by benvanik • Draft
Reapply "[GPU] Allow multi result and indexing compute generic ops in TilleAndFuse pipeline" (#22205)"
#22223 opened Oct 6, 2025 by nirvedhmeshram Loading…
2
Carry encoding in the preferred storage type of a hoistable type
#22221 opened Oct 6, 2025 by jtuyls Loading…
5
[debugging][gpu] Add --iree-rocm-debug-symbols flag
#22216 opened Oct 6, 2025 by willghatch Loading…
4
[PkgCI] Use urllib instead of github cli in pkgci artifact_run
#22211 opened Oct 6, 2025 by Groverkss Loading…
1
[codegen][gpu] Make transfer_write conditional when not fully distributed
#22198 opened Oct 3, 2025 by newling Loading…
11
[Stream] Deduplicate the dispatch workloads
#22187 opened Oct 2, 2025 by jtuyls Loading…
10
[GPU][DT] Refactor tile size selection for narrow matmul
#22177 opened Oct 1, 2025 by Yu-Zhewen • Draft
1
1
[Codegen][LLVMGPU] Strategy for when reduction dim isn't contiguous
#22172 opened Oct 1, 2025 by newling Loading…
10
Increase acceptable error in punet
#22169 opened Oct 1, 2025 by newling Loading…
[Codegen] Tile memref.copy when vectorizing for dynamic dims
#22168 opened Oct 1, 2025 by jtuyls Loading…
9
Transposed Workgroup Reordering for large rectangular matmuls
#22165 opened Oct 1, 2025 by sebvince Loading…
49
[Codegen] Implement the mechanism to lower bufferized CoalescedDMA op
#22158 opened Sep 30, 2025 by lialan • Draft
31
[Codegen] Add a pass to unrol n-d vectors to 1-d vectors
#22156 opened Sep 30, 2025 by Groverkss • Draft
[Do Not Submit] Disable all const expr hoisting.
#22151 opened Sep 29, 2025 by MaheshRavishankar • Draft
[docs] Add LLVM debugging and some AMDGPU-specific tips documentation ✏️ Improvements or additions to documentation
#22146 opened Sep 29, 2025 by krzysz00 Loading…
32
Fix the splitReduction pass
#22138 opened Sep 28, 2025 by FlintWangacc Loading…
6
[Codegen][GPU] update the tuning spec using new transform ops
#22134 opened Sep 27, 2025 by bangtianliu Loading…
3
[LLVMCPU] Refactor multi lowering config propagation and setting
#22126 opened Sep 26, 2025 by Yu-Zhewen Loading…
1
7
Rewriting CombineInitializersPass to not make incorrect programs. compiler/dialects Relating to the IREE compiler dialects (flow, hal, vm)
#22118 opened Sep 26, 2025 by benvanik • Draft
ProTip! Exclude everything labeled bug with -label:bug.
0