8000 shared/runtime/gchelper: Add RISC-V RV32I native gchelper. · davidgiven/micropython@de0e13a · GitHub
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shared/runtime/gchelper: Add RISC-V RV32I native gchelper.
Add native gchelper support for 32 bits RISC-V RV32I targets. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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‎shared/runtime/gchelper.h

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@@ -41,6 +41,8 @@ typedef uintptr_t gc_helper_regs_t[4];
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typedef uintptr_t gc_helper_regs_t[10];
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#elif defined(__aarch64__)
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typedef uintptr_t gc_helper_regs_t[11]; // x19-x29
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#elif defined(__riscv) && defined(__riscv_xlen) && (__riscv_xlen == 32)
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typedef uintptr_t gc_helper_regs_t[12]; // S0-S11
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#endif
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#endif

‎shared/runtime/gchelper_generic.c

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@@ -150,6 +150,37 @@ static void gc_helper_get_regs(gc_helper_regs_t arr) {
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arr[10] = x29;
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}
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#elif defined(__riscv) && defined(__riscv_xlen) && (__riscv_xlen == 32)
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// Fallback implementation for RV32I, prefer gchelper_rv32i.s
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static void gc_helper_get_regs(gc_helper_regs_t arr) {
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register long s0 asm ("x8");
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register long s1 asm ("x9");
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register long s2 asm ("x18");
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register long s3 asm ("x19");
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register long s4 asm ("x20");
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register long s5 asm ("x21");
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register long s6 asm ("x22");
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register long s7 asm ("x23");
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register long s8 asm ("x24");
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register long s9 asm ("x25");
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register long s10 asm ("x26");
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register long s11 asm ("x27");
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arr[0] = s0;
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arr[1] = s1;
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arr[2] = s2;
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arr[3] = s3;
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arr[4] = s4;
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arr[5] = s5;
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arr[6] = s6;
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arr[7] = s7;
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arr[8] = s8;
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arr[9] = s9;
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arr[10] = s10;
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arr[11] = s11;
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}
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#else
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#error "Architecture not supported for gc_helper_get_regs. Set MICROPY_GCREGS_SETJMP to use the fallback implementation."

‎shared/runtime/gchelper_rv32i.s

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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2024 Alessandro Gatti
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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.global gc_helper_get_regs_and_sp
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.type gc_helper_get_regs_and_sp, @function
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gc_helper_get_regs_and_sp:
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/* Store registers into the given array. */
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sw x8, 0(x10) /* Save S0. */
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sw x9, 4(x10) /* Save S1. */
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sw x18, 8(x10) /* Save S2. */
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sw x19, 12(x10) /* Save S3. */
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sw x20, 16(x10) /* Save S4. */
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sw x21, 20(x10) /* Save S5. */
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sw x22, 24(x10) /* Save S6. */
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sw x23, 28(x10) /* Save S7. */
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sw x24, 32(x10) /* Save S8. */
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sw x25, 36(x10) /* Save S9. */
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sw x26, 40(x10) /* Save S10. */
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sw x27, 44(x10) /* Save S11. */
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/* Return the stack pointer. */
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add x10, x0, x2
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jalr x0, x1, 0
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.size gc_helper_get_regs_and_sp, .-gc_helper_get_regs_and_sp

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