8000 py/nlrrv32: Add RISC-V RV32I NLR implementation. · davidgiven/micropython@e6ae699 · GitHub
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py/nlrrv32: Add RISC-V RV32I NLR implementation.
Add custom NLR support for 32 bits RISC-V RV32I targets. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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‎py/nlr.h

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#define MICROPY_NLR_NUM_REGS_MIPS (13)
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#define MICROPY_NLR_NUM_REGS_XTENSA (10)
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#define MICROPY_NLR_NUM_REGS_XTENSAWIN (17)
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#define MICROPY_NLR_NUM_REGS_RV32I (14)
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// *FORMAT-OFF*
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#elif defined(__mips__)
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#define MICROPY_NLR_MIPS (1)
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#define MICROPY_NLR_NUM_REGS (MICROPY_NLR_NUM_REGS_MIPS)
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#elif defined(__riscv) && defined(__riscv_xlen) && (__riscv_xlen == 32)
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#define MICROPY_NLR_RV32I (1)
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#define MICROPY_NLR_NUM_REGS (MICROPY_NLR_NUM_REGS_RV32I)
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#else
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#define MICROPY_NLR_SETJMP (1)
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//#warning "No native NLR support for this arch, using setjmp implementation"

‎py/nlrrv32.c

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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2024 Alessandro Gatti
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/mpstate.h"
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#if MICROPY_NLR_RV32I
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#undef nlr_push
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__attribute__((naked)) unsigned int nlr_push(nlr_buf_t *nlr) {
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__asm volatile (
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"sw x1, 8(x10) \n" // Store RA.
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"sw x8, 12(x10) \n" // Store S0.
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"sw x9, 16(x10) \n" // Store S1.
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"sw x18, 20(x10) \n" // Store S2.
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"sw x19, 24(x10) \n" // Store S3.
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"sw x20, 28(x10) \n" // Store S4.
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"sw x21, 32(x10) \n" // Store S5.
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"sw x22, 36(x10) \n" // Store S6.
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"sw x23, 40(x10) \n" // Store S7.
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"sw x24, 44(x10) \n" // Store S8.
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"sw x25, 48(x10) \n" // Store S9.
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"sw x26, 52(x10) \n" // Store S10.
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"sw x27, 56(x10) \n" // Store S11.
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"sw x2, 60(x10) \n" // Store SP.
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"jal x0, nlr_push_tail \n" // Jump to the C part.
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);
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}
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NORETURN void nlr_jump(void *val) {
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MP_NLR_JUMP_HEAD(val, top)
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__asm volatile (
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"add x10, x0, %0 \n" // Load nlr_buf address.
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"lw x1, 8(x10) \n" // Retrieve RA.
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"lw x8, 12(x10) \n" // Retrieve S0.
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"lw x9, 16(x10) \n" // Retrieve S1.
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"lw x18, 20(x10) \n" // Retrieve S2.
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"lw x19, 24(x10) \n" // Retrieve S3.
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"lw x20, 28(x10) \n" // Retrieve S4.
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"lw x21, 32(x10) \n" // Retrieve S5.
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"lw x22, 36(x10) \n" // Retrieve S6.
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"lw x23, 40(x10) \n" // Retrieve S7.
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"lw x24, 44(x10) \n" // Retrieve S8.
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"lw x25, 48(x10) \n" // Retrieve S9.
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"lw x26, 52(x10) \n" // Retrieve S10.
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"lw x27, 56(x10) \n" // Retrieve S11.
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"lw x2, 60(x10) \n" // Retrieve SP.
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"addi x10, x0, 1 \n" // Return 1 for a non-local return.
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"jalr x0, x1, 0 \n" // Return.
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: // Outputs.
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: "r" (top) // Inputs.
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: "memory" // Clobbered.
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);
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MP_UNREACHABLE
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}
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#endif // MICROPY_NLR_RV32I

‎py/py.cmake

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${MICROPY_PY_DIR}/nlr.c
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${MICROPY_PY_DIR}/nlrmips.c
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${MICROPY_PY_DIR}/nlrpowerpc.c
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${MICROPY_PY_DIR}/nlrrv32.c
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${MICROPY_PY_DIR}/nlrsetjmp.c
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${MICROPY_PY_DIR}/nlrthumb.c
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${MICROPY_PY_DIR}/nlrx64.c

‎py/py.mk

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nlrmips.o \
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nlrpowerpc.o \
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nlrxtensa.o \
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nlrrv32.o \
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nlrsetjmp.o \
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malloc.o \
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gc.o \

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