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8000 GitHub · Where software is built

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parameter optimization in terms of AXI ADDR WIDTH

#247

· Zyy439 opened

on Nov 19, 2025

How to plugin verilog-ethernet in corundum design ?

#246

· lizajoseph opened

on Nov 13, 2025

kernel panic on mqnic_process_rx_cq

#245

· GbGp opened

on Oct 14, 2025

How to effectively change the num of TX queues to 8K as suggested? any constraints on FPGA boards?

#244

· Winters123 opened

on Jun 26, 2025

Alveo U280 network bandwidth

#243

· lifeis-hard opened

on Jun 19, 2025

In some cases, when PCIE performs Non-Posted Request, CplH exceeds the limit and cannot be recovered.

#242

· chen0228 opened

on Jun 17, 2025

Alveo U280 - Trouble with Performance

#240

· JefferyLim opened

on May 31, 2025

Implicit behaviour of AXI streams in app block?

#234

· harris-chris opened

on Apr 15, 2025

How to port Corundum to the Intel Agilex® 7 FPGA I-Series

#233

· xingyunzhidi opened

on Apr 14, 2025

Will XC7Z015-CLG485ABX21 be supported?

#228

· ting2985 opened

on Dec 30, 2024

Support for dmabuf between corundum and a GPU (Direct p2p between GPU and FPGA)

#227

· dandaly opened

on Dec 24, 2024

Change clk period to meet timing constraints

#226

· MarioPatetta opened

on Dec 9, 2024

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