10000 Merge tag 'drm-intel-next-fixes-2015-04-25' of git://anongit.freedesk… · bsd-unix/linux@59fd7e4 · GitHub
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Merge tag 'drm-intel-next-fixes-2015-04-25' of git://anongit.freedesktop.org/drm-intel into drm-fixes
three fixes for i915. * tag 'drm-intel-next-fixes-2015-04-25' of git://anongit.freedesktop.org/drm-intel: drm/i915: vlv: fix save/restore of GFX_MAX_REQ_COUNT reg drm/i915: Workaround to avoid lite restore with HEAD==TAIL drm/i915: cope with large i2c transfers
2 parents c8b3fd0 + b5f1c97 commit 59fd7e4

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lines changed

‎drivers/gpu/drm/i915/i915_drv.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1038,7 +1038,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
10381038
s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
10391039

10401040
s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1041-
s->gfx_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1041+
s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
10421042

10431043
s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
10441044
s->ecochk = I915_READ(GAM_ECOCHK);
@@ -1120,7 +1120,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
11201120
I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
11211121

11221122
I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1123-
I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1123+
I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
11241124

11251125
I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
11261126
I915_WRITE(GAM_ECOCHK, s->ecochk);

‎drivers/gpu/drm/i915/i915_gem.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2377,10 +2377,11 @@ int __i915_add_request(struct intel_engine_cs *ring,
23772377
ret = ring->add_request(ring);
23782378
if (ret)
23792379
return ret;
2380+
2381+
request->tail = intel_ring_get_tail(ringbuf);
23802382
}
23812383

23822384
request->head = request_start;
2383-
request->tail = intel_ring_get_tail(ringbuf);
23842385

23852386
/* Whilst this request exists, batch_obj will be on the
23862387
* active_list, and so will hold the active reference. Only when this

‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1807,6 +1807,7 @@ enum skl_disp_power_wells {
18071807
#define GMBUS_CYCLE_INDEX (2<<25)
18081808
#define GMBUS_CYCLE_STOP (4<<25)
18091809
#define GMBUS_BYTE_COUNT_SHIFT 16
1810+
#define GMBUS_BYTE_COUNT_MAX 256U
18101811
#define GM 8000 BUS_SLAVE_INDEX_SHIFT 8
18111812
#define GMBUS_SLAVE_ADDR_SHIFT 1
18121813
#define GMBUS_SLAVE_READ (1<<0)

‎drivers/gpu/drm/i915/intel_i2c.c

Lines changed: 56 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -270,18 +270,17 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
270270
}
271271

272272
static int
273-
gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
274-
u32 gmbus1_index)
273+
gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
274+
unsigned short addr, u8 *buf, unsigned int len,
275+
u32 gmbus1_index)
275276
{
276277
int reg_offset = dev_priv->gpio_mmio_base;
277-
u16 len = msg->len;
278-
u8 *buf = msg->buf;
279278

280279
I915_WRITE(GMBUS1 + reg_offset,
281280
gmbus1_index |
282281
GMBUS_CYCLE_WAIT |
283282
(len << GMBUS_BYTE_COUNT_SHIFT) |
284-
(msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
283+
(addr << GMBUS_SLAVE_ADDR_SHIFT) |
285284
GMBUS_SLAVE_READ | GMBUS_SW_RDY);
286285
while (len) {
287286
int ret;
@@ -303,11 +302,35 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
303302
}
304303

305304
static int
306-
gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
305+
gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
306+
u32 gmbus1_index)
307307
{
308-
int reg_offset = dev_priv->gpio_mmio_base;
309-
u16 len = msg->len;
310308
u8 *buf = msg->buf;
309+
unsigned int rx_size = msg->len;
310+
unsigned int len;
311+
int ret;
312+
313+
do {
314+
len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
315+
316+
ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
317+
buf, len, gmbus1_index);
318+
if (ret)
319+
return ret;
320+
321+
rx_size -= len;
322+
buf += len;
323+
} while (rx_size != 0);
324+
325+
return 0;
326+
}
327+
328+
static int
329+
gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
330+
unsigned short addr, u8 *buf, unsigned int len)
331+
{
332+
int reg_offset = dev_priv->gpio_mmio_base;
333+
unsigned int chunk_size = len;
311334
u32 val, loop;
312335

313336
val = loop = 0;
@@ -319,8 +342,8 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
319342
I915_WRITE(GMBUS3 + reg_offset, val);
320343
I915_WRITE(GMBUS1 + reg_offset,
321344
GMBUS_CYCLE_WAIT |
322-
(msg->len << GMBUS_BYTE_COUNT_SHIFT) |
323-
(msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
345+
(chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
346+
(addr << GMBUS_SLAVE_ADDR_SHIFT) |
324347
GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
325348
while (len) {
326349
int ret;
@@ -337,6 +360,29 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
337360
if (ret)
338361
return ret;
339362
}
363+
364+
return 0;
365+
}
366+
367+
static int
368+
gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
369+
{
370+
u8 *buf = msg->buf;
371+
unsigned int tx_size = msg->len;
372+
unsigned int len;
373+
int ret;
374+
375+
do {
376+
len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
377+
378+
ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len);
379+
if (ret)
380+
return ret;
381+
382+
buf += len;
383+
tx_size -= len;
384+
} while (tx_size != 0);
385+
340386
return 0;
341387
}
342388

‎drivers/gpu/drm/i915/intel_lrc.c

Lines changed: 34 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -393,6 +393,26 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring)
393393
}
394394
}
395395

396+
if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
397+
/*
398+
* WaIdleLiteRestore: make sure we never cause a lite
399+
* restore with HEAD==TAIL
400+
*/
401+
if (req0 && req0->elsp_submitted) {
402+
/*
403+
* Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
404+
* as we resubmit the request. See gen8_emit_request()
405+
* for where we prepare the padding after the end of the
406+
* request.
407+
*/
408+
struct intel_ringbuffer *ringbuf;
409+
410+
ringbuf = req0->ctx->engine[ring->id].ringbuf;
411+
req0->tail += 8;
412+
req0->tail &= ringbuf->size - 1;
413+
}
414+
}
415+
396416
WARN_ON(req1 && req1->elsp_submitted);
397417

398418
execlists_submit_contexts(ring, req0->ctx, req0->tail,
@@ -1315,7 +1335,12 @@ static int gen8_emit_request(struct intel_ringbuffer *ringbuf,
13151335
u32 cmd;
13161336
int ret;
13171337

1318-
ret = intel_logical_ring_begin(ringbuf, request->ctx, 6);
1338+
/*
1339+
* Reserve space for 2 NOOPs at the end of each request to be
1340+
* used as a workaround for not being allowed to do lite
1341+
* restore with HEAD==TAIL (WaIdleLiteRestore).
1342+
*/
1343+
ret = intel_logical_ring_begin(ringbuf, request->ctx, 8);
13191344
if (ret)
13201345
return ret;
13211346

@@ -1333,6 +1358,14 @@ static int gen8_emit_request(struct intel_ringbuffer *ringbuf,
13331358
intel_logical_ring_emit(ringbuf, MI_NOOP);
13341359
intel_logical_ring_advance_and_submit(ringbuf, request->ctx, request);
13351360

1361+
/*
1362+
* Here we add two extra NOOPs as padding to avoid
1363+
* lite restore of a context with HEAD==TAIL.
1364+
*/
1365+
intel_logical_ring_emit(ringbuf, MI_NOOP);
1366+
intel_logical_ring_emit(ringbuf, MI_NOOP);
1367+
intel_logical_ring_advance(ringbuf);
1368+
13361369
return 0;
13371370
}
13381371

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