Discussions

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  InOut in Signature

  tclarke asked Sep 25, 2024 in Q&A · Answered

  

  

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  How to correctly write top module with multiple modules and I/O ports

  TarikHamedovic asked Aug 6, 2024 in Q&A · Unanswered

  

  

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  GateMate Support With Amaranth

  TarikHamedovic asked May 31, 2024 in Q&A · Answered

  

  

  

  

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  Can you simulate a purely combinatorial module in Amaranth

  TarikHamedovic asked Jun 11, 2024 in Q&A · Closed · Answered

  

  

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  Idea: lib.wiring and the Transactron library of Coreblocks

  tilk started May 23, 2024 in Ideas

  

  

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  Returning the signal name map when generating Verilog code

  xThaid asked Jan 29, 2024 in Q&A · Answered

  

  

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  How to convert numpy arrays into Const() lookup tables

  jrmoserbaltimore asked Jan 27, 2024 in Q&A · Unanswered

  

  

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  nextpnr-ecp5 not in path

  TarikHamedovic asked Nov 30, 2023 in Q&A · Answered

  

  

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  agregate Signal()

  jalcim asked Sep 28, 2023 in Q&A · Unanswered

  

  

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