Electrical Engineering & Physics student at Sogang University.
Interested in hardware–software co-design for efficient computing systems, including FPGA accelerators, embedded platforms, and edge AI.
INT8 systolic-array accelerator implemented on a Zynq SoC with full HW–SW co-design.
Key aspects:
- RTL implementation of a systolic array architecture
- AXI-based memory interface
- System-level performance analysis and bottleneck investigation
Experiments on post-training quantization (PTQ) and quantization-aware training (QAT) for efficient edge deployment.
Embedded firmware development using STM32, including sensor interfacing, ADC data acquisition, and peripheral control.
- FPGA & Hardware Acceleration
- Embedded Systems
- Edge AI Deployment
- System Performance Analysis