Stars
Rust library to parse SystemVerilog / Verilog filelists, used in https://github.com/dalance/svlint
Verilog evaluation benchmark for large language model
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Control and status register code generator toolchain
CUDD: CU Decision Diagram package - unofficial git mirror of https://web.archive.org/web/20180127051756/http://vlsi.colorado.edu/~fabio/CUDD/html/index.html (intro: https://web.archive.org/web/2015…
fakeram generator for use by researchers who do not have access to commercial ram generators
Perform historical snapshots without database locks and read change data capture logs from databases. Artie Reader is compatible with Debezium and is written in Go.
Database replication platform that leverages change data capture. Stream production data from databases to your data warehouse (Snowflake, BigQuery, Redshift) in real-time.
A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
EDA-centric utility for linting and analyzing Tcl code.
An open-source Ternary Content Addressable Memory (TCAM) compiler.
Yosys plugin for logic locking and supply-chain security
Nuitka is a Python compiler written in Python. It's fully compatible with Python 2.6, 2.7, 3.4-3.12. You feed it your Python app, it does a lot of clever things, and spits out an executable or exte…
An elegant Python implementation to convert Liberty library format into JSON format
Ghidra is a software reverse engineering (SRE) framework
An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model