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Added support for my new FeatherS2 Neo esp32s2 board #5287
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61 changes: 61 additions & 0 deletions
61
ports/esp32s2/boards/unexpectedmaker_feathers2_neo/board.c
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,61 @@ | ||
| /* | ||
| * This file is part of the MicroPython project, http://micropython.org/ | ||
| * | ||
| * The MIT License (MIT) | ||
| * | ||
| * Copyright (c) 2020 Scott Shawcroft for Adafruit Industries | ||
| * | ||
| * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
| * of this software and associated documentation files (the "Software"), to deal | ||
| * in the Software without restriction, including without limitation the rights | ||
| * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
| * copies of the Software, and to permit persons to whom the Software is | ||
| * furnished to do so, subject to the following conditions: | ||
| * | ||
| * The above copyright notice and this permission notice shall be included in | ||
| * all copies or substantial portions of the Software. | ||
| * | ||
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE | ||
| * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
| * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
| * THE SOFTWARE. | ||
| */ | ||
|
|
||
| #include "supervisor/board.h" | ||
| #include "mpconfigboard.h" | ||
| #include "shared-bindings/microcontroller/Pin.h" | ||
|
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| void board_init(void) { | ||
| // USB | ||
| common_hal_never_reset_pin(&pin_GPIO19); | ||
| common_hal_never_reset_pin(&pin_GPIO20); | ||
|
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| // Debug UART | ||
| #ifdef DEBUG | ||
| common_hal_never_reset_pin(&pin_GPIO43); | ||
| common_hal_never_reset_pin(&pin_GPIO44); | ||
| #endif /* DEBUG */ | ||
|
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| // SPI Flash and RAM | ||
| common_hal_never_reset_pin(&pin_GPIO26); | ||
| common_hal_never_reset_pin(&pin_GPIO27); | ||
| common_hal_never_reset_pin(&pin_GPIO28); | ||
| common_hal_never_reset_pin(&pin_GPIO29); | ||
| common_hal_never_reset_pin(&pin_GPIO30); | ||
| common_hal_never_reset_pin(&pin_GPIO31); | ||
| common_hal_never_reset_pin(&pin_GPIO32); | ||
| } | ||
|
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| bool board_requests_safe_mode(void) { | ||
| return false; | ||
| } | ||
|
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| void reset_board(void) { | ||
|
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| } | ||
|
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| void board_deinit(void) { | ||
| } |
47 changes: 47 additions & 0 deletions
47
ports/esp32s2/boards/unexpectedmaker_feathers2_neo/mpconfigboard.h
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,47 @@ | ||
| /* | ||
| * This file is part of the MicroPython project, http://micropython.org/ | ||
| * | ||
| * The MIT License (MIT) | ||
| * | ||
| * Copyright (c) 2019 Scott Shawcroft for Adafruit Industries | ||
| * | ||
| * Permission is hereby granted, free of charge, to any person obtaining a copy | ||
| * of this software and associated documentation files (the "Software"), to deal | ||
| * in the Software without restriction, including without limitation the rights | ||
| * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | ||
| * copies of the Software, and to permit persons to whom the Software is | ||
| * furnished to do so, subject to the following conditions: | ||
| * | ||
| * The above copyright notice and this permission notice shall be included in | ||
| * all copies or substantial portions of the Software. | ||
| * | ||
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE | ||
| * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | ||
| * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | ||
| * THE SOFTWARE. | ||
| */ | ||
|
|
||
| // Micropython setup | ||
|
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| #define MICROPY_HW_BOARD_NAME "FeatherS2 Neo" | ||
| #define MICROPY_HW_MCU_NAME "ESP32S2" | ||
|
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| #define MICROPY_HW_NEOPIXEL (&pin_GPIO40) | ||
| #define CIRCUITPY_STATUS_LED_POWER (&pin_GPIO39) | ||
| #define CIRCUITPY_BOOT_BUTTON (&pin_GPIO0) | ||
| #define BOARD_USER_SAFE_MODE_ACTION translate("pressing boot button at start up.\n") | ||
|
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| #define AUTORESET_DELAY_MS 500 | ||
|
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| #define DEFAULT_I2C_BUS_SCL (&pin_GPIO9) | ||
| #define DEFAULT_I2C_BUS_SDA (&pin_GPIO8) | ||
|
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| #define DEFAULT_SPI_BUS_SCK (&pin_GPIO36) | ||
| #define DEFAULT_SPI_BUS_MOSI (&pin_GPIO35) | ||
| #define DEFAULT_SPI_BUS_MISO (&pin_GPIO37) | ||
|
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| #define DEFAULT_UART_BUS_RX (&pin_GPIO44) | ||
| #define DEFAULT_UART_BUS_TX (&pin_GPIO43) |
20 changes: 20 additions & 0 deletions
20
ports/esp32s2/boards/unexpectedmaker_feathers2_neo/mpconfigboard.mk
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,20 @@ | ||
| USB_VID = 0x239A | ||
| USB_PID = 0x80B5 | ||
| USB_PRODUCT = "FeatherS2 Neo" | ||
| USB_MANUFACTURER = "UnexpectedMaker" | ||
|
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| INTERNAL_FLASH_FILESYSTEM = 1 | ||
| LONGINT_IMPL = MPZ | ||
|
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| # The default queue depth of 16 overflows on release builds, | ||
| # so increase it to 32. | ||
| CFLAGS += -DCFG_TUD_TASK_QUEUE_SZ=32 | ||
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| CIRCUITPY_ESP_FLASH_MODE=qio | ||
| CIRCUITPY_ESP_FLASH_FREQ=80m | ||
| CIRCUITPY_ESP_FLASH_SIZE=4MB | ||
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| CIRCUITPY_BITBANG_NEOPIXEL = 1 | ||
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| # Include these Python libraries in firmware. | ||
| FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_NeoPixel | ||
119 changes: 119 additions & 0 deletions
119
ports/esp32s2/boards/unexpectedmaker_feathers2_neo/pins.c
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,119 @@ | ||
| #include "shared-bindings/board/__init__.h" | ||
|
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| STATIC const mp_rom_map_elem_t board_global_dict_table[] = { | ||
| { MP_ROM_QSTR(MP_QSTR_IO0), MP_ROM_PTR(&pin_GPIO0) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO0) }, | ||
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| { MP_ROM_QSTR(MP_QSTR_IO17), MP_ROM_PTR(&pin_GPIO17) }, | ||
| { MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO17) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO17) }, | ||
| { MP_ROM_QSTR(MP_QSTR_DAC1), MP_ROM_PTR(&pin_GPIO17) }, | ||
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| { MP_ROM_QSTR(MP_QSTR_IO18), MP_ROM_PTR(&pin_GPIO18) }, | ||
| { MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO18) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO18) }, | ||
| { MP_ROM_QSTR(MP_QSTR_DAC2), MP_ROM_PTR(&pin_GPIO18) }, | ||
|
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||
| { MP_ROM_QSTR(MP_QSTR_IO14), MP_ROM_PTR(&pin_GPIO14) }, | ||
| { MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO14) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_GPIO14) }, | ||
|
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||
| { MP_ROM_QSTR(MP_QSTR_IO12), MP_ROM_PTR(&pin_GPIO12) }, | ||
| { MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO12) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_GPIO12) }, | ||
|
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||
| { MP_ROM_QSTR(MP_QSTR_IO6), MP_ROM_PTR(&pin_GPIO6) }, | ||
| { MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO6) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_GPIO6) }, | ||
|
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||
| { MP_ROM_QSTR(MP_QSTR_IO5), MP_ROM_PTR(&pin_GPIO5) }, | ||
| { MP_ROM_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO5) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D19), MP_ROM_PTR(&pin_GPIO5) }, | ||
|
|
||
| { MP_ROM_QSTR(MP_QSTR_IO36), MP_ROM_PTR(&pin_GPIO36) }, | ||
| { MP_ROM_QSTR(MP_QSTR_SCK), MP_ROM_PTR(&pin_GPIO36) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D25), MP_ROM_PTR(&pin_GPIO36) }, | ||
|
|
||
| { MP_ROM_QSTR(MP_QSTR_IO35), MP_ROM_PTR(&pin_GPIO35) }, | ||
| { MP_ROM_QSTR(MP_QSTR_MOSI), MP_ROM_PTR(&pin_GPIO35) }, | ||
| { MP_ROM_QSTR(MP_QSTR_SDO), MP_ROM_PTR(&pin_GPIO35) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D24), MP_ROM_PTR(&pin_GPIO35) }, | ||
|
|
||
| { MP_ROM_QSTR(MP_QSTR_IO37), MP_ROM_PTR(&pin_GPIO37) }, | ||
| { MP_ROM_QSTR(MP_QSTR_MISO), MP_ROM_PTR(&pin_GPIO37) }, | ||
| { MP_ROM_QSTR(MP_QSTR_SDI), MP_ROM_PTR(&pin_GPIO37) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D23), MP_ROM_PTR(&pin_GPIO37) }, | ||
|
|
||
| { MP_ROM_QSTR(MP_QSTR_IO44), MP_ROM_PTR(&pin_GPIO44) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO44) }, | ||
| { MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO44) }, | ||
|
|
||
| { MP_ROM_QSTR(MP_QSTR_IO43), MP_ROM_PTR(&pin_GPIO43) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO43) }, | ||
| { MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO43) }, | ||
|
|
||
| { MP_ROM_QSTR(MP_QSTR_IO45), MP_ROM_PTR(&pin_GPIO45) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO45) }, | ||
|
|
||
| { MP_ROM_QSTR(MP_QSTR_IO8), MP_ROM_PTR(&pin_GPIO8) }, | ||
| { MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO8) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_GPIO8) }, | ||
|
|
||
| { MP_ROM_QSTR(MP_QSTR_IO9), MP_ROM_PTR(&pin_GPIO9) }, | ||
| { MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO9) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D22), MP_ROM_PTR(&pin_GPIO9) }, | ||
|
|
||
| { MP_ROM_QSTR(MP_QSTR_IO33), MP_ROM_PTR(&pin_GPIO33) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO33) }, | ||
|
|
||
| { MP_ROM_QSTR(MP_QSTR_IO38), MP_ROM_PTR(&pin_GPIO38) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO38) }, | ||
|
|
||
|
|
||
| { MP_ROM_QSTR(MP_QSTR_IO1), MP_ROM_PTR(&pin_GPIO1) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO1) }, | ||
| { MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_GPIO1) }, | ||
|
|
||
| { MP_ROM_QSTR(MP_QSTR_IO3), MP_ROM_PTR(&pin_GPIO3) }, | ||
| 6D47 | { MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO3) }, | |
| { MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_GPIO3) }, | ||
|
|
||
| { MP_ROM_QSTR(MP_QSTR_IO7), MP_ROM_PTR(&pin_GPIO7) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO7) }, | ||
| { MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_GPIO7) }, | ||
|
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||
| { MP_ROM_QSTR(MP_QSTR_IO10), MP_ROM_PTR(&pin_GPIO10) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO10) }, | ||
| { MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_GPIO10) }, | ||
|
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| { MP_ROM_QSTR(MP_QSTR_IO11), MP_ROM_PTR(&pin_GPIO11) }, | ||
| { MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO11) }, | ||
| { MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_GPIO11) }, | ||
|
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||
| { MP_ROM_QSTR(MP_QSTR_IO13), MP_ROM_PTR(&pin_GPIO13) }, // Blue LED | ||
| { MP_ROM_QSTR(MP_QSTR_LED), MP_ROM_PTR(&pin_GPIO13) }, // Blue LED | ||
|
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||
| { MP_ROM_QSTR(MP_QSTR_BATTERY), MP_ROM_PTR(&pin_GPIO2) }, | ||
| { MP_ROM_QSTR(MP_QSTR_VBAT), MP_ROM_PTR(&pin_GPIO2) }, | ||
| { MP_ROM_QSTR(MP_QSTR_VBAT_SENSE), MP_ROM_PTR(&pin_GPIO2) }, | ||
| { MP_ROM_QSTR(MP_QSTR_VOLTAGE_MONITOR), MP_ROM_PTR(&pin_GPIO2) }, | ||
|
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| // 5V present sense pin | ||
| { MP_ROM_QSTR(MP_QSTR_VBUS), MP_ROM_PTR(&pin_GPIO34) }, | ||
| { MP_ROM_QSTR(MP_QSTR_VBUS_SENSE), MP_ROM_PTR(&pin_GPIO34) }, | ||
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| { MP_ROM_QSTR(MP_QSTR_NEOPIXEL_POWER), MP_ROM_PTR(&pin_GPIO39) }, | ||
| { MP_ROM_QSTR(MP_QSTR_IO39), MP_ROM_PTR(&pin_GPIO39) }, | ||
| { MP_ROM_QSTR(MP_QSTR_NEOPIXEL), MP_ROM_PTR(&pin_GPIO40) }, | ||
| { MP_ROM_QSTR(MP_QSTR_IO40), MP_ROM_PTR(&pin_GPIO40) }, | ||
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| { MP_ROM_QSTR(MP_QSTR_NEOPIXEL_MATRIX_POWER), MP_ROM_PTR(&pin_GPIO4) }, | ||
| { MP_ROM_QSTR(MP_QSTR_IO4), MP_ROM_PTR(&pin_GPIO4) }, | ||
| { MP_ROM_QSTR(MP_QSTR_NEOPIXEL_MATRIX), MP_ROM_PTR(&pin_GPIO21) }, | ||
| { MP_ROM_QSTR(MP_QSTR_IO21), MP_ROM_PTR(&pin_GPIO21) }, | ||
|
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| { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) }, | ||
| { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj) }, | ||
| { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) }, | ||
| }; | ||
| MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); |
39 changes: 39 additions & 0 deletions
39
ports/esp32s2/boards/unexpectedmaker_feathers2_neo/sdkconfig
9E81
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,39 @@ | ||
| CONFIG_ESP32S2_SPIRAM_SUPPORT=y | ||
|
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| # | ||
| # SPI RAM config | ||
| # | ||
| # CONFIG_SPIRAM_TYPE_AUTO=y | ||
| CONFIG_SPIRAM_TYPE_ESPPSRAM16=y | ||
| # CONFIG_SPIRAM_TYPE_ESPPSRAM32 is not set | ||
| # CONFIG_SPIRAM_TYPE_ESPPSRAM64=y | ||
| CONFIG_SPIRAM_SIZE=2097152 | ||
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| # | ||
| # PSRAM clock and cs IO for ESP32S2 | ||
| # | ||
| CONFIG_DEFAULT_PSRAM_CLK_IO=30 | ||
| CONFIG_DEFAULT_PSRAM_CS_IO=26 | ||
| # end of PSRAM clock and cs IO for ESP32S2 | ||
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| # CONFIG_SPIRAM_FETCH_INSTRUCTIONS is not set | ||
| # CONFIG_SPIRAM_RODATA is not set | ||
| # CONFIG_SPIRAM_SPEED_80M is not set | ||
| CONFIG_SPIRAM_SPEED_40M=y | ||
| # CONFIG_SPIRAM_SPEED_26M is not set | ||
| # CONFIG_SPIRAM_SPEED_20M is not set | ||
| CONFIG_SPIRAM=y | ||
| CONFIG_SPIRAM_BOOT_INIT=y | ||
| # CONFIG_SPIRAM_IGNORE_NOTFOUND is not set | ||
| CONFIG_SPIRAM_USE_MEMMAP=y | ||
| # CONFIG_SPIRAM_USE_CAPS_ALLOC is not set | ||
| # CONFIG_SPIRAM_USE_MALLOC is not set | ||
| CONFIG_SPIRAM_MEMTEST=y | ||
| # CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set | ||
| # end of SPI RAM config | ||
|
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| # | ||
| # LWIP | ||
| # | ||
| CONFIG_LWIP_LOCAL_HOSTNAME="UMFeatherS2Neo" | ||
| # end of LWIP |
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