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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,93 @@ | ||
| """Primitive constant field tests.""" | ||
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| from unittest import TestCase | ||
| from ..testbench import RegisterFileTestbench | ||
|
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| class TestPrimitiveConstantFields(TestCase): | ||
| """Primitive constant field tests""" | ||
|
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| def test_fields(self): | ||
| """test constant fields""" | ||
| rft = RegisterFileTestbench({ | ||
| 'metadata': {'name': 'test'}, | ||
| 'fields': [ | ||
| { | ||
| 'address': '0x--', | ||
| 'name': 'a', | ||
| 'behavior': 'axi', | ||
| 'flatten': True | ||
| }, | ||
| ]}) | ||
| self.assertEqual(rft.ports, ('bus', 'f_a')) | ||
| with rft as objs: | ||
|
|
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| # Test blocking. | ||
| read_resp = [] | ||
| def read_cb(_, resp): | ||
| read_resp.append(int(resp)) | ||
| objs.bus.async_read(read_cb, 0) | ||
|
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| write_resp = [] | ||
| def write_cb(resp): | ||
| write_resp.append(int(resp)) | ||
| objs.bus.async_write(write_cb, 0, 0) | ||
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| rft.testbench.clock(20) | ||
| self.assertEqual(read_resp, []) | ||
| self.assertEqual(write_resp, []) | ||
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| objs.f_a.start() | ||
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| rft.testbench.clock(10) | ||
| self.assertEqual(read_resp, [0]) | ||
| self.assertEqual(write_resp, [0]) | ||
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| # Test data passthrough. | ||
| for i in range(16): | ||
| objs.bus.write(i * 4, hash(str(i)) & 0xFFFFFFFF) | ||
| for i in range(16): | ||
| self.assertEqual(objs.f_a.read(i * 4), hash(str(i)) & 0xFFFFFFFF) | ||
| self.assertEqual(objs.bus.read(i * 4), hash(str(i)) & 0xFFFFFFFF) | ||
|
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| # Test error passthrough. | ||
| objs.f_a.handle_read = lambda *_: 'error' | ||
| objs.f_a.handle_write = lambda *_: 'error' | ||
| with self.assertRaisesRegex(ValueError, 'slave'): | ||
| objs.bus.read(0) | ||
| with self.assertRaisesRegex(ValueError, 'slave'): | ||
| objs.bus.write(0, 0) | ||
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| objs.f_a.handle_read = lambda *_: 'decode' | ||
| objs.f_a.handle_write = lambda *_: 'decode' | ||
| with self.assertRaisesRegex(ValueError, 'decode'): | ||
| objs.bus.read(0) | ||
| with self.assertRaisesRegex(ValueError, 'decode'): | ||
| objs.bus.write(0, 0) | ||
|
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| def test_errors(self): | ||
| """test constant field config errors""" | ||
| msg = ('AXI fields must be 32 or 64 bits wide') | ||
| with self.assertRaisesRegex(Exception, msg): | ||
| RegisterFileTestbench({ | ||
| 'metadata': {'name': 'test'}, | ||
| 'fields': [ | ||
| { | ||
| 'address': 0, | ||
| 'bitrange': '15..0', | ||
| 'name': 'a', | ||
| 'behavior': 'axi', | ||
| }, | ||
| ]}) | ||
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| msg = ('subaddress is too wide for 30-bit word address') | ||
| with self.assertRaisesRegex(Exception, msg): | ||
| RegisterFileTestbench({ | ||
| 'metadata': {'name': 'test'}, | ||
| 'fields': [ | ||
| { | ||
| 'address': 0, | ||
| 'subaddress': [{'blank': 40}], | ||
| 'name': 'a', | ||
| 'behavior': 'axi', | ||
| }, | ||
| ]}) |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,77 @@ | ||
| """Submodule for AXI behavior.""" | ||
|
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| from .base import Behavior, behavior, BusAccessNoOpMethod, BusAccessBehavior, BusBehavior | ||
| from ...config.behavior import Axi | ||
|
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| @behavior(Axi) | ||
| class AxiBehavior(Behavior): | ||
| """Behavior class for AXI fields.""" | ||
|
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| def __init__(self, resources, field_descriptor, | ||
| behavior_cfg, read_allow_cfg, write_allow_cfg): | ||
|
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| # Figure out the bus width. | ||
| bus_width = field_descriptor.base_bitrange.width | ||
| if bus_width not in [32, 64]: | ||
| raise ValueError('AXI fields must be 32 or 64 bits wide') | ||
|
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| # Figure out the slice of the bus address that is controlled by the | ||
| # subaddress. | ||
| sub_low = {32: 2, 64: 3}[bus_width] | ||
| sub_high = sub_low + field_descriptor.subaddress.width - 1 | ||
| if sub_high > 31: | ||
| raise ValueError( | ||
| 'subaddress is too wide for %d-bit word address' | ||
| % (32 - sub_low)) | ||
| self._subaddress_range = '%s downto %d' % (sub_high, sub_low) | ||
|
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| # Connect the internal signal for the interrupt. | ||
| self._interrupt_internal = None | ||
| if behavior_cfg.interrupt_internal is not None: | ||
| self._interrupt_internal = resources.internals.drive( | ||
| field_descriptor, | ||
| behavior_cfg.interrupt_internal, | ||
| field_descriptor.shape) | ||
|
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| # Decode the bus access behavior. | ||
| if behavior_cfg.mode in ['read-only', 'read-write']: | ||
| read_behavior = BusAccessBehavior( | ||
| read_allow_cfg, | ||
| blocking=True, volatile=True, deferring=True, | ||
| no_op_method=BusAccessNoOpMethod.NEVER) | ||
| else: | ||
| read_behavior = None | ||
|
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| if behavior_cfg.mode in ['write-only', 'read-write']: | ||
| write_behavior = BusAccessBehavior( | ||
| write_allow_cfg, | ||
| blocking=True, volatile=True, deferring=True, | ||
| no_op_method=BusAccessNoOpMethod.NEVER) | ||
| else: | ||
| write_behavior = None | ||
|
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| bus_behavior = BusBehavior( | ||
| read=read_behavior, write=write_behavior, | ||
| can_read_for_rmw=False) | ||
|
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| super().__init__(field_descriptor, behavior_cfg, bus_behavior) | ||
|
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| @property | ||
| def interrupt_internal(self): | ||
| """The internal signal used for the interrupt signal that `vhdmmio` | ||
| passes along with AXI4L busses, or `None` if this signal is not | ||
| used.""" | ||
| return self._interrupt_internal | ||
|
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| @property | ||
| def subaddress_range(self): | ||
| """The slice of the child bus address in VHDL range notation that the | ||
| subaddress maps to.""" | ||
| return self._subaddress_range | ||
|
|
||
| @property | ||
| def doc_reset(self): | ||
| """The reset value as printed in the documentation as an integer, or | ||
| `None` if the field is driven by a signal and thus does not have a | ||
| register to reset.""" | ||
| return None |
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