stm32f103xb_hic: Use CMSIS UART driver from CDC ACM

ARMmbed · mbrossard · Oct 30, 2021 · Feb 1, 2023 · Feb 2, 2023 · Jan 14, 2022
commit 1bea3a308cd5b45d03ef17b02912d648874a15db
diff --git a/records/hic_hal/stm32f103xb.yaml b/records/hic_hal/stm32f103xb.yaml
@@ -22,6 +22,7 @@ common:
             - source/hic_hal/stm32/stm32f103xb
             - source/hic_hal/stm32/stm32f103xb/cmsis
             - source/hic_hal/stm32/stm32f103xb/STM32F1xx_HAL_Driver/Src
+            - source/hic_hal/cmsis-driver/uart/uart.c
 
 tool_specific:
     uvision:

diff --git a/source/hic_hal/stm32/stm32f103xb/IO_Config.h b/source/hic_hal/stm32/stm32f103xb/IO_Config.h
@@ -82,5 +82,9 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_STM32F103XB);
 #define PIN_MSC_LED                  GPIO_PIN_9
 #define PIN_MSC_LED_Bit              9
 
+#include "Driver_USART.h"
+extern ARM_DRIVER_USART Driver_USART2;
+#define CMSIS_UART_INSTANCE          (Driver_USART2)
+#define CMSIS_UART_IRQ               (USART2_IRQn)
 
 #endif
diff --git a/source/hic_hal/stm32/stm32f103xb/RTE_Device.h b/source/hic_hal/stm32/stm32f103xb/RTE_Device.h
@@ -213,10 +213,10 @@
 
 // <e> USART2 (Universal synchronous asynchronous receiver transmitter)
 // <i> Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART
-#define RTE_USART2                      0
+#define RTE_USART2                      1
 
 //   <o> USART2_TX Pin <0=>Not Used <1=>PA2
-#define RTE_USART2_TX_PORT_ID_DEF       0
+#define RTE_USART2_TX_PORT_ID_DEF       1
 #if    (RTE_USART2_TX_PORT_ID_DEF == 0)
 #define RTE_USART2_TX_DEF               0
 #elif  (RTE_USART2_TX_PORT_ID_DEF == 1)
@@ -228,7 +228,7 @@
 #endif
 
 //   <o> USART2_RX Pin <0=>Not Used <1=>PA3
-#define RTE_USART2_RX_PORT_ID_DEF       0
+#define RTE_USART2_RX_PORT_ID_DEF       1
 #if    (RTE_USART2_RX_PORT_ID_DEF == 0)
 #define RTE_USART2_RX_DEF               0
 #elif  (RTE_USART2_RX_PORT_ID_DEF == 1)
@@ -404,350 +404,4 @@
 
 // </e>
 
-
-// <e> USART3 (Universal synchronous asynchronous receiver transmitter)
-// <i> Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART
-#define RTE_USART3                      0
-
-//   <o> USART3_TX Pin <0=>Not Used <1=>PB10
-#define RTE_USART3_TX_PORT_ID_DEF       0
-#if    (RTE_USART3_TX_PORT_ID_DEF == 0)
-#define RTE_USART3_TX_DEF               0
-#elif  (RTE_USART3_TX_PORT_ID_DEF == 1)
-#define RTE_USART3_TX_DEF               1
-#define RTE_USART3_TX_PORT_DEF          GPIOB
-#define RTE_USART3_TX_BIT_DEF           10
-#else
-#error "Invalid USART3_TX Pin Configuration!"
-#endif
-
-//   <o> USART3_RX Pin <0=>Not Used <1=>PB11
-#define RTE_USART3_RX_PORT_ID_DEF       0
-#if    (RTE_USART3_RX_PORT_ID_DEF == 0)
-#define RTE_USART3_RX_DEF               0
-#elif  (RTE_USART3_RX_PORT_ID_DEF == 1)
-#define RTE_USART3_RX_DEF               1
-#define RTE_USART3_RX_PORT_DEF          GPIOB
-#define RTE_USART3_RX_BIT_DEF           11
-#else
-#error "Invalid USART3_RX Pin Configuration!"
-#endif
-
-//   <o> USART3_CK Pin <0=>Not Used <1=>PB12
-#define RTE_USART3_CK_PORT_ID_DEF       0
-#if    (RTE_USART3_CK_PORT_ID_DEF == 0)
-#define RTE_USART3_CK_DEF               0
-#elif  (RTE_USART3_CK_PORT_ID_DEF == 1)
-#define RTE_USART3_CK_DEF               1
-#define RTE_USART3_CK_PORT_DEF          GPIOB
-#define RTE_USART3_CK_BIT_DEF           12
-#else
-#error "Invalid USART3_CK Pin Configuration!"
-#endif
-
-//   <o> USART3_CTS Pin <0=>Not Used <1=>PB13
-#define RTE_USART3_CTS_PORT_ID_DEF      0
-#if    (RTE_USART3_CTS_PORT_ID_DEF == 0)
-#define RTE_USART3_CTS_DEF              0
-#elif  (RTE_USART3_CTS_PORT_ID_DEF == 1)
-#define RTE_USART3_CTS_DEF              1
-#define RTE_USART3_CTS_PORT_DEF         GPIOB
-#define RTE_USART3_CTS_BIT_DEF          13
-#else
-#error "Invalid USART3_CTS Pin Configuration!"
-#endif
-
-//   <o> USART3_RTS Pin <0=>Not Used <1=>PB14
-#define RTE_USART3_RTS_PORT_ID_DEF      0
-#if    (RTE_USART3_RTS_PORT_ID_DEF == 0)
-#define RTE_USART3_RTS_DEF              0
-#elif  (RTE_USART3_RTS_PORT_ID_DEF == 1)
-#define RTE_USART3_RTS_DEF              1
-#define RTE_USART3_RTS_PORT_DEF         GPIOB
-#define RTE_USART3_RTS_BIT_DEF          14
-#else
-#error "Invalid USART3_RTS Pin Configuration!"
-#endif
-
-//   <e> USART3 Partial Pin Remap
-//   <i> Enable USART3 Partial Pin Remapping
-#define RTE_USART3_REMAP_PARTIAL        0
-
-//     <o> USART3_TX Pin <0=>Not Used <1=>PC10
-#define RTE_USART3_TX_PORT_ID_PARTIAL   0
-#if    (RTE_USART3_TX_PORT_ID_PARTIAL == 0)
-#define RTE_USART3_TX_PARTIAL           0
-#elif  (RTE_USART3_TX_PORT_ID_PARTIAL == 1)
-#define RTE_USART3_TX_PARTIAL           1
-#define RTE_USART3_TX_PORT_PARTIAL      GPIOC
-#define RTE_USART3_TX_BIT_PARTIAL       10
-#else
-#error "Invalid USART3_TX Pin Configuration!"
-#endif
-
-//     <o> USART3_RX Pin <0=>Not Used <1=>PC11
-#define RTE_USART3_RX_PORT_ID_PARTIAL   0
-#if    (RTE_USART3_RX_PORT_ID_PARTIAL == 0)
-#define RTE_USART3_RX_PARTIAL           0
-#elif  (RTE_USART3_RX_PORT_ID_PARTIAL == 1)
-#define RTE_USART3_RX_PARTIAL           1
-#define RTE_USART3_RX_PORT_PARTIAL      GPIOC
-#define RTE_USART3_RX_BIT_PARTIAL       11
-#else
-#error "Invalid USART3_RX Pin Configuration!"
-#endif
-
-//     <o> USART3_CK Pin <0=>Not Used <1=>PC12
-#define RTE_USART3_CK_PORT_ID_PARTIAL   0
-#if    (RTE_USART3_CK_PORT_ID_PARTIAL == 0)
-#define RTE_USART3_CK_PARTIAL           0
-#elif  (RTE_USART3_CK_PORT_ID_PARTIAL == 1)
-#define RTE_USART3_CK_PARTIAL           1
-#define RTE_USART3_CK_PORT_PARTIAL      GPIOC
-#define RTE_USART3_CK_BIT_PARTIAL       12
-#else
-#error "Invalid USART3_CK Pin Configuration!"
-#endif
-//   </e>
-
-//   <e> USART3 Full Pin Remap
-//   <i> Enable USART3 Full Pin Remapping
-#define RTE_USART3_REMAP_FULL           0
-
-//     <o> USART3_TX Pin <0=>Not Used <1=>PD8
-#define RTE_USART3_TX_PORT_ID_FULL      0
-#if    (RTE_USART3_TX_PORT_ID_FULL == 0)
-#define RTE_USART3_TX_FULL              0
-#elif  (RTE_USART3_TX_PORT_ID_FULL == 1)
-#define RTE_USART3_TX_FULL              1
-#define RTE_USART3_TX_PORT_FULL         GPIOD
-#define RTE_USART3_TX_BIT_FULL          8
-#else
-#error "Invalid USART3_TX Pin Configuration!"
-#endif
-
-//     <o> USART3_RX Pin <0=>Not Used <1=>PD9
-#define RTE_USART3_RX_PORT_ID_FULL      0
-#if    (RTE_USART3_RX_PORT_ID_FULL == 0)
-#define RTE_USART3_RX_FULL              0
-#elif  (RTE_USART3_RX_PORT_ID_FULL == 1)
-#define RTE_USART3_RX_FULL              1
-#define RTE_USART3_RX_PORT_FULL         GPIOD
-#define RTE_USART3_RX_BIT_FULL          9
-#else
-#error "Invalid USART3_RX Pin Configuration!"
-#endif
-
-//     <o> USART3_CK Pin <0=>Not Used <1=>PD10
-#define RTE_USART3_CK_PORT_ID_FULL      0
-#if    (RTE_USART3_CK_PORT_ID_FULL == 0)
-#define RTE_USART3_CK_FULL              0
-#elif  (RTE_USART3_CK_PORT_ID_FULL == 1)
-#define RTE_USART3_CK_FULL              1
-#define RTE_USART3_CK_PORT_FULL         GPIOD
-#define RTE_USART3_CK_BIT_FULL          10
-#else
-#error "Invalid USART3_CK Pin Configuration!"
-#endif
-
-//     <o> USART3_CTS Pin <0=>Not Used <1=>PD11
-#define RTE_USART3_CTS_PORT_ID_FULL     0
-#if    (RTE_USART3_CTS_PORT_ID_FULL == 0)
-#define RTE_USART3_CTS_FULL             0
-#elif  (RTE_USART3_CTS_PORT_ID_FULL == 1)
-#define RTE_USART3_CTS_FULL             1
-#define RTE_USART3_CTS_PORT_FULL        GPIOD
-#define RTE_USART3_CTS_BIT_FULL         11
-#else
-#error "Invalid USART3_CTS Pin Configuration!"
-#endif
-
-//     <o> USART3_RTS Pin <0=>Not Used <1=>PD12
-#define RTE_USART3_RTS_PORT_ID_FULL     0
-#if    (RTE_USART3_RTS_PORT_ID_FULL == 0)
-#define RTE_USART3_RTS_FULL             0
-#elif  (RTE_USART3_RTS_PORT_ID_FULL == 1)
-#define RTE_USART3_RTS_FULL             1
-#define RTE_USART3_RTS_PORT_FULL        GPIOD
-#define RTE_USART3_RTS_BIT_FULL         12
-#else
-#error "Invalid USART3_RTS Pin Configuration!"
-#endif
-//   </e>
-
-#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1))
-#error "Invalid USART3 Pin Remap Configuration!"
-#endif
-
-#if    (RTE_USART3_REMAP_FULL)
-#define RTE_USART3_AF_REMAP              AFIO_USART3_REMAP_FULL
-#define RTE_USART3_TX                    RTE_USART3_TX_FULL
-#define RTE_USART3_TX_PORT               RTE_USART3_TX_PORT_FULL
-#define RTE_USART3_TX_BIT                RTE_USART3_TX_BIT_FULL
-#define RTE_USART3_RX                    RTE_USART3_RX_FULL
-#define RTE_USART3_RX_PORT               RTE_USART3_RX_PORT_FULL
-#define RTE_USART3_RX_BIT                RTE_USART3_RX_BIT_FULL
-#define RTE_USART3_CK                    RTE_USART3_CK_FULL
-#define RTE_USART3_CK_PORT               RTE_USART3_CK_PORT_FULL
-#define RTE_USART3_CK_BIT                RTE_USART3_CK_BIT_FULL
-#define RTE_USART3_CTS                   RTE_USART3_CTS_FULL
-#define RTE_USART3_CTS_PORT              RTE_USART3_CTS_PORT_FULL
-#define RTE_USART3_CTS_BIT               RTE_USART3_CTS_BIT_FULL
-#define RTE_USART3_RTS                   RTE_USART3_RTS_FULL
-#define RTE_USART3_RTS_PORT              RTE_USART3_RTS_PORT_FULL
-#define RTE_USART3_RTS_BIT               RTE_USART3_RTS_BIT_FULL
-#elif  (RTE_USART3_REMAP_PARTIAL)
-#define RTE_USART3_AF_REMAP              AFIO_USART3_REMAP_PARTIAL
-#define RTE_USART3_TX                    RTE_USART3_TX_PARTIAL
-#define RTE_USART3_TX_PORT               RTE_USART3_TX_PORT_PARTIAL
-#define RTE_USART3_TX_BIT                RTE_USART3_TX_BIT_PARTIAL
-#define RTE_USART3_RX                    RTE_USART3_RX_PARTIAL
-#define RTE_USART3_RX_PORT               RTE_USART3_RX_PORT_PARTIAL
-#define RTE_USART3_RX_BIT                RTE_USART3_RX_BIT_PARTIAL
-#define RTE_USART3_CK                    RTE_USART3_CK_PARTIAL
-#define RTE_USART3_CK_PORT               RTE_USART3_CK_PORT_PARTIAL
-#define RTE_USART3_CK_BIT                RTE_USART3_CK_BIT_PARTIAL
-#define RTE_USART3_CTS                   RTE_USART3_CTS_DEF
-#define RTE_USART3_CTS_PORT              RTE_USART3_CTS_PORT_DEF
-#define RTE_USART3_CTS_BIT               RTE_USART3_CTS_BIT_DEF
-#define RTE_USART3_RTS                   RTE_USART3_RTS_DEF
-#define RTE_USART3_RTS_PORT              RTE_USART3_RTS_PORT_DEF
-#define RTE_USART3_RTS_BIT               RTE_USART3_RTS_BIT_DEF
-#else
-#define RTE_USART3_AF_REMAP              AFIO_USART3_NO_REMAP
-#define RTE_USART3_TX                    RTE_USART3_TX_DEF
-#define RTE_USART3_TX_PORT               RTE_USART3_TX_PORT_DEF
-#define RTE_USART3_TX_BIT                RTE_USART3_TX_BIT_DEF
-#define RTE_USART3_RX                    RTE_USART3_RX_DEF
-#define RTE_USART3_RX_PORT               RTE_USART3_RX_PORT_DEF
-#define RTE_USART3_RX_BIT                RTE_USART3_RX_BIT_DEF
-#define RTE_USART3_CK                    RTE_USART3_CK_DEF
-#define RTE_USART3_CK_PORT               RTE_USART3_CK_PORT_DEF
-#define RTE_USART3_CK_BIT                RTE_USART3_CK_BIT_DEF
-#define RTE_USART3_CTS                   RTE_USART3_CTS_DEF
-#define RTE_USART3_CTS_PORT              RTE_USART3_CTS_PORT_DEF
-#define RTE_USART3_CTS_BIT               RTE_USART3_CTS_BIT_DEF
-#define RTE_USART3_RTS                   RTE_USART3_RTS_DEF
-#define RTE_USART3_RTS_PORT              RTE_USART3_RTS_PORT_DEF
-#define RTE_USART3_RTS_BIT               RTE_USART3_RTS_BIT_DEF
-#endif
-
-//   <e> DMA Rx
-//     <o1> Number <1=>1
-//     <i>  Selects DMA Number (only DMA1 can be used)
-//     <o2> Channel <3=>3
-//     <i>  Selects DMA Channel (only Channel 3 can be used)
-//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-//     <i>  Sets DMA Channel priority
-//   </e>
-#define RTE_USART3_RX_DMA               0
-#define RTE_USART3_RX_DMA_NUMBER        1
-#define RTE_USART3_RX_DMA_CHANNEL       3
-#define RTE_USART3_RX_DMA_PRIORITY      0
-
-//   <e> DMA Tx
-//     <o1> Number <1=>1
-//     <i>  Selects DMA Number (only DMA1 can be used)
-//     <o2> Channel <2=>2
-//     <i>  Selects DMA Channel (only Channel 2 can be used)
-//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-//     <i>  Sets DMA Channel priority
-//   </e>
-#define RTE_USART3_TX_DMA               0
-#define RTE_USART3_TX_DMA_NUMBER        1
-#define RTE_USART3_TX_DMA_CHANNEL       2
-#define RTE_USART3_TX_DMA_PRIORITY      0
-
-// </e>
-
-
-// <e> UART4 (Universal asynchronous receiver transmitter)
-// <i> Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART
-#define RTE_UART4                       0
-#define RTE_UART4_AF_REMAP              AFIO_UNAVAILABLE_REMAP
-
-//   <o> UART4_TX Pin <0=>Not Used <1=>PC10
-#define RTE_UART4_TX_ID                 0
-#if    (RTE_UART4_TX_ID == 0)
-#define RTE_UART4_TX                    0
-#elif  (RTE_UART4_TX_ID == 1)
-#define RTE_UART4_TX                    1
-#define RTE_UART4_TX_PORT               GPIOC
-#define RTE_UART4_TX_BIT                10
-#else
-#error "Invalid UART4_TX Pin Configuration!"
-#endif
-
-//   <o> UART4_RX Pin <0=>Not Used <1=>PC11
-#define RTE_UART4_RX_ID                 0
-#if    (RTE_UART4_RX_ID == 0)
-#define RTE_UART4_RX                    0
-#elif  (RTE_UART4_RX_ID == 1)
-#define RTE_UART4_RX                    1
-#define RTE_UART4_RX_PORT               GPIOC
-#define RTE_UART4_RX_BIT                11
-#else
-#error "Invalid UART4_RX Pin Configuration!"
-#endif
-
-
-//   <e> DMA Rx
-//     <o1> Number <2=>2
-//     <i>  Selects DMA Number (only DMA2 can be used)
-//     <o2> Channel <3=>3
-//     <i>  Selects DMA Channel (only Channel 3 can be used)
-//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-//     <i>  Sets DMA Channel priority
-//   </e>
-#define RTE_UART4_RX_DMA                0
-#define RTE_UART4_RX_DMA_NUMBER         2
-#define RTE_UART4_RX_DMA_CHANNEL        3
-#define RTE_UART4_RX_DMA_PRIORITY       0
-
-//   <e> DMA Tx
-//     <o1> Number <2=>2
-//     <i>  Selects DMA Number (only DMA2 can be used)
-//     <o2> Channel <5=>5
-//     <i>  Selects DMA Channel (only Channel 5 can be used)
-//     <o3> Priority <0=>Low <1=>Medium <2=>High <3=>Very high
-//     <i>  Sets DMA Channel priority
-//   </e>
-#define RTE_UART4_TX_DMA                0
-#define RTE_UART4_TX_DMA_NUMBER         2
-#define RTE_UART4_TX_DMA_CHANNEL        5
-#define RTE_UART4_TX_DMA_PRIORITY       0
-
-// </e>
-
-
-// <e> UART5 (Universal asynchronous receiver transmitter)
-// <i> Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART
-#define RTE_UART5                       0
-#define RTE_UART5_AF_REMAP              AFIO_UNAVAILABLE_REMAP
-
-//   <o> UART5_TX Pin <0=>Not Used <1=>PC12
-#define RTE_UART5_TX_ID                 0
-#if    (RTE_UART5_TX_ID == 0)
-#define RTE_UART5_TX                    0
-#elif  (RTE_UART5_TX_ID == 1)
-#define RTE_UART5_TX                    1
-#define RTE_UART5_TX_PORT               GPIOC
-#define RTE_UART5_TX_BIT                12
-#else
-#error "Invalid UART5_TX Pin Configuration!"
-#endif
-
-//   <o> UART5_RX Pin <0=>Not Used <1=>PD2
-#define RTE_UART5_RX_ID                 0
-#if    (RTE_UART5_RX_ID == 0)
-#define RTE_UART5_RX                    0
-#elif  (RTE_UART5_RX_ID == 1)
-#define RTE_UART5_RX                    1
-#define RTE_UART5_RX_PORT               GPIOD
-#define RTE_UART5_RX_BIT                2
-#else
-#error "Invalid UART5_RX Pin Configuration!"
-#endif
-// </e>
-
 #endif  /* __RTE_DEVICE_H */