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5 nm process

In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the "5 nm" process as the MOSFET technology node following the "7 nm" node. In 2020, Samsung and TSMC entered volume production of "5 nm" chips, manufactured for companies including Apple, Huawei, Mediatek, Qualcomm and Marvell.[1][2]

The term "5 nm" does not indicate that any physical feature (such as gate length, metal pitch or gate pitch) of the transistors is five nanometers in size. Historically, the number used in the name of a technology node represented the gate length, but it started deviating from the actual length to smaller numbers (by Intel) around 2011.[3] According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, the 5 nm node is expected to have a gate length of 18nm, a contacted gate pitch of 51nm, and a tightest metal pitch of 30nm.[4] In real world commercial practice, "5 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption compared to the previous 7 nm process.[5][6]

History

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Background

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Quantum tunnelling effects through the gate oxide layer on "7 nm" and "5 nm" transistors became increasingly difficult to manage using existing semiconductor processes.[7] Single-transistor devices below 7 nm were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6-nanometre silicon-on-insulator (SOI) MOSFET.[8][9]

In 2003, a Japanese research team at NEC, led by Hitoshi Wakabayashi and Shigeharu Yamagami, fabricated the first 5 nm MOSFET.[10][11]

In 2015, IMEC and Cadence fabricated 5 nm test chips. The fabricated test chips were not fully functional devices, but rather are to evaluate patterning of interconnect layers.[12][13]

In 2015, Intel described a lateral nanowire (or gate-all-around) FET concept for the "5 nm" node.[14]

In 2017, IBM revealed that it had created "5 nm" silicon chips,[15] using silicon nanosheets in a gate-all-around configuration (GAAFET), a break from the usual FinFET design. The GAAFET transistors used had 3 nanosheets stacked on top of each other, covered in their entirety by the same gate, just like FinFETs usually have several physical fins side by side that are electrically a single unit and are covered in their entirety by the same gate. IBM's chip measured 50 mm2 and had 600 million transistors per mm2, for a total of 30 billion transistors (1667 nm2 per transistor or 41 nm actual transistor spacing).[16][17]

Commercialization

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In April 2019, Samsung Electronics announced they had been offering their "5 nm" process (5LPE) tools to their customers since 2018 Q4.[18] In April 2019, TSMC announced that their "5 nm" process (CLN5FF, N5) had begun risk production, and that full chip design specifications were now available to potential customers. The N5 process can use EUVL on up to 14 layers, compared to only 5 or 4 layers in N6 and N7++.[19] For the expected 28 nm minimum metal pitch, SALELE is the proposed best patterning method.[20]

For their "5 nm" process, Samsung started process defect mitigation by automated check and fix, due to occurrence of stochastic (random) defects in the metal and via layers.[21]

In October 2019, TSMC reportedly started sampling 5 nm A14 processors for Apple.[22] At the 2020 IEEE IEDM conference, TSMC reported their 5 nm process had 1.84x higher density than their 7nm process.[23] At IEDM 2019, TSMC revealed two versions of 5 nm, a DUV version with a 5.5-track cell, and an (official) EUV version with a 6-track cell.[24][25]

In December 2019, TSMC announced an average yield of approximately 80%, with a peak yield per wafer of over 90% for their "5 nm" test chips with a die size of 17.92 mm2.[26] In mid 2020 TSMC claimed its (N5) "5 nm" process offered 1.8x the density of its "7 nm" N7 process, with 15% speed improvement or 30% lower power consumption; an improved sub-version (N5P or N4) was claimed to improve on N5 with +5% speed or -10% power.[27]

On 13 October 2020, Apple announced a new iPhone 12 lineup using the A14. Together with the Huawei Mate 40 lineup using the HiSilicon Kirin 9000, the A14 and Kirin 9000 were the first devices to be commercialized on TSMC's "5 nm" node. Later, on 10 November 2020, Apple also revealed three new Mac models using the Apple M1, another 5 nm chip. According to Semianalysis, the A14 processor has a transistor density of 134 million transistors per mm2.[28]

In October 2021, TSMC introduced a new member of its "5 nm" process family: N4P. Compared to N5, the node offered 11% higher performance (6% higher vs N4), 22% higher power efficiency, 6% higher transistor density and lower mask count. TSMC expected first tapeouts by the second half of 2022.[29][30][needs update]

In December 2021, TSMC announced a new member of its "5 nm" process family designed for HPC applications: N4X. The process featured optimized transistor design and structures, reduced resistance and capacitance of targeted metal layers and high-density MiM capacitors. The process was expected at that time to[needs update] offer up to 15% higher performance vs N5 (or up to 4% vs N4P) at 1.2 V and supply voltage in excess of 1.2 V. TSMC, at that time, said that they expected[needs update] N4X to enter risk production by the first half of 2023.[31][32][33]

In June 2022, Intel presented some details about the Intel 4 process (known as "7 nm" before renaming in 2021): the company's first process to use EUV, 2x higher transistor density compared to Intel 7 (known as "10 nm" ESF (Enhanced Super Fin) before the renaming), use of cobalt-clad copper for the finest five layers of interconnect, 21.5% higher performance at iso power or 40% lower power at iso frequency at 0.65 V compared to Intel 7 etc. Intel's first product to be fabbed on Intel 4 was Meteor Lake, powered on in Q2 2022 and scheduled for shipping in 2023.[34] Intel 4 has contacted gate pitch of 50 nm, both fin and minimum metal pitch of 30 nm, and library height of 240 nm. Metal-insulator-metal capacitance was increased to 376 fF/μm², roughly 2x compared to Intel 7.[35] The process was optimized for HPC applications and supported voltage from <0.65 V to >1.3 V. WikiChip's transistor density estimate for Intel 4 was 123.4 Mtr./mm², 2.04x from 60.5 Mtr./mm² for Intel 7. However, high-density SRAM cell had scaled only by 0.77x (from 0.0312 to 0.024 μm²) and high-performance cell by 0.68x (from 0.0441 to 0.03 μm²) compared to Intel 7.[36][needs update]

On 27 September 2022, AMD officially launched their Ryzen 7000 series of central processing units, based on the TSMC N5 process and Zen 4 microarchitecture.[37] Zen 4 marked the first utilization of the 5 nm process for x86-based desktop processors. In December 2022 AMD also launched the Radeon RX 7000 series of graphics processing units based on RDNA 3, which also used the TSMC N5 process.[38]

Nodes

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5 nm
IRDS roadmap 2017[39] Samsung[40][41][42][43][44] TSMC[40]
Process name 7 nm 5 nm 5LPE 5LPP N5 N5P 4N[45]
Transistor density (MTr/mm2) Un­known Un­known 126.9[44] Un­known 138.2[46][47] Unknown
SRAM bit-cell size (μm2) 0.027[48] 0.020[48] 0.0262[49] 0.021[49] Unknown
Transistor gate pitch (nm) 48 42 57 51 Unknown
Interconnect pitch (nm) 28 24 36 Un­known 28[50] Unknown
Release status 2019 2021 2018 risk production[18]
2020 production 		2022 production 2019 risk production[19]
2020 production 		2020 risk production
2021 production 		2022 production

4 nm process nodes

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Samsung[40][42][43][44][51] TSMC Intel[52][34]
Process name 4LPE
SF4E		 4LPP
SF4		 4LPP+
SF4P		 4HPC
SF4X		 4LPA
SF4U 		N4 N4P N4X[31][32][33] N4C[53] 4[54][55]
Transistor density (MTr/mm2) 137[44] Un­known Un­known Un­known 143.7[56] Un­known Un­known 123.4[36]
SRAM bit-cell size (μm2) 0.0262[49] Un­known Un­known Un­known Un­known Un­known Un­known 0.024[49]
Transistor gate pitch (nm) 57 Un­known Un­known Un­known 51 Un­known Un­known 50
Interconnect pitch (nm) 32 Un­known Un­known Un­known 28 Un­known Un­known 30
Release status 2020 risk production
2021 production		 2022 production 2023 production 2024 production 2025 production 2021 risk production
2022 production		 2022 risk production
2022 production		 Risk production by H1 2023
2024 production		 2025 production 2022 risk production[57]
2023 production[58]

Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch).[59][60]

Beyond 4 nm

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Main article: 3 nm process

"3 nm" is the usual term for the next node after "5 nm". As of 2023, TSMC has started producing chips for select customers, while Samsung and Intel have plans for 2024.[52][61][62][63]

"3.5 nm" has also been given as a name for the first node beyond "5 nm".[64]

References

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Preceded by
"7 nm" (FinFET) 		MOSFET semiconductor device fabrication process Succeeded by
"3 nm" (FinFET/GAAFET)
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