An Instruction Set Extension to Support Software-Based Masking

Authors

  • Si Gao Alpen-Adria Universität Klagenfurt, Klagenfurt, Austria
  • Johann Großschädl Department of Computer Science, University of Luxembourg, Luxembourg, Luxembourg
  • Ben Marshall Department of Computer Science, University of Bristol, Bristol, UK; PQShield Ltd, Oxford, UK
  • Dan Page Department of Computer Science, University of Bristol, Bristol, UK
  • Thinh Pham Department of Computer Science, University of Bristol, Bristol, UK
  • Francesco Regazzoni UniversitÃa della Svizzera italiana, Lugano, Switzerland

DOI:

https://doi.org/10.46586/tches.v2021.i4.283-325

Keywords:

side-channel attack, masking, RISC-V, ISE

Abstract

In both hardware and software, masking can represent an effective means of hardening an implementation against side-channel attack vectors such as Differential Power Analysis (DPA). Focusing on software, however, the use of masking can present various challenges: specifically, it often 1) requires significant effort to translate any theoretical security properties into practice, and, even then, 2) imposes a significant overhead in terms of efficiency. To address both challenges, this paper explores the use of an Instruction Set Extension (ISE) to support masking in software-based implementations of a range of (symmetric) cryptographic kernels including AES: we design, implement, and evaluate such an ISE, using RISC-V as the base ISA. Our ISE-supported first-order masked implementation of AES, for example, is an order of magnitude more efficient than a software-only alternative with respect to both execution latency and memory footprint; this renders it comparable to an unmasked implementation using the same metrics, but also first-order secure.

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Published

2021-08-11

Issue

Section

Articles

How to Cite

An Instruction Set Extension to Support Software-Based Masking. (2021). IACR Transactions on Cryptographic Hardware and Embedded Systems, 2021(4), 283-325. https://doi.org/10.46586/tches.v2021.i4.283-325