A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors
"> Figure 1
<p>Block diagram of a linear image sensor.</p> "> Figure 2
<p>(<b>a</b>) The structure of CTIA; (<b>b</b>) The output curve of CTIA.</p> "> Figure 3
<p>Switch sequence of the offset cancellation scheme. (<b>a</b>) Reset state; (<b>b</b>) <span class="html-italic">ϕ</span><sub>rst(1)</sub> is switched off; (<b>c</b>) <span class="html-italic">ϕ</span><sub>rst(2)</sub> is switched off; (<b>d</b>) <span class="html-italic">ϕ</span><sub>rst(3)</sub> is switched from <span class="html-italic">V</span><sub>ref</sub> to the output terminal; (<b>e</b>) <span class="html-italic">I</span><sub>ph</sub> starts to integrate on <span class="html-italic">C</span><sub>int</sub>.</p> "> Figure 4
<p>Circuit diagram of CTIA.</p> "> Figure 5
<p>(<b>a</b>) Block diagram of ATC; (<b>b</b>) Timing diagram of ATC.</p> "> Figure 6
<p>Block diagram of proposed TDC.</p> "> Figure 7
<p>Timing diagram of proposed TDC.</p> "> Figure 8
<p>Block diagram of VDL and DLL.</p> "> Figure 9
<p>Timing diagrams of the TDC illustrating quantization error sources. (<b>a</b>) Δ<span class="html-italic">T</span><sub>p</sub> < 0; (<b>b</b>) Δ<span class="html-italic">T</span><sub>p</sub> > 0.</p> "> Figure 10
<p>Timing diagram of the proposed calibration circuit. (<b>a</b>) <span class="html-italic">ST</span><sub>1</sub> rises at the low level state of clock; (<b>b</b>) <span class="html-italic">ST</span><sub>1</sub> rises at the high level state of clock (<span class="html-italic">C_ideal</span> denotes the ideal output of coarse quantization; <span class="html-italic">C_real</span> denotes the actual output of coarse quantization).</p> "> Figure 11
<p>Block diagram of the proposed calibration circuit.</p> "> Figure 12
<p>Layout of the linear image sensor.</p> "> Figure 13
<p>Output voltage <span class="html-italic">versus</span> photocurrent. The pixel saturates at around 12.5 μA.</p> "> Figure 14
<p>The transient simulation of the pixel integration.</p> "> Figure 15
<p>Quantization error without calibration. (<b>a</b>) −<span class="html-italic">T</span><sub>clk</sub> < Δ<span class="html-italic">T</span><sub>p</sub> < −<span class="html-italic">T</span><sub>clk</sub>/2; (<b>b</b>) −<span class="html-italic">T</span><sub>clk</sub>/2 < Δ<span class="html-italic">T</span><sub>p</sub> < −100 ps; (<b>c</b>) −100ps < Δ<span class="html-italic">T</span><sub>p</sub> < 0.</p> "> Figure 16
<p>DNL and INL with calibration.</p> "> Figure 17
<p>ADC output spectrum. (<b>a</b>) Without calibration; (<b>b</b>) With calibration.</p> "> Figure 18
<p>The linearity of the proposed image sensor</p> ">
Abstract
:1. Introduction
2. Dynamic Range Enhanced Readout Circuit
2.1. Capacitor Trans-Impedance Amplifier (CTIA)
2.1.1. Offset Cancellation
2.1.2. Dynamic Range Extension
2.2. Readout Circuits Implementation
2.2.1. OPA Design
2.2.2. Logic Control and Comparator Design
3. Design of Column-Level ADC with Two-Step TDC
3.1. Operation Principle
3.2. ATC
3.3. TDC
3.4. Quantization Error and Calibration
4. Results
4.1. Readout Circuits
4.2. ADC
Without Calibration | With Calibration | |
---|---|---|
SFDR(@470.7031k), SNDR(@470.7031k) | 64.17 dB 46.18 dB | 70.18 dB 60.22 dB |
ENOB(@470.7031k) | 7.31 bit | 9.71 bit |
SFDR(@1.9531k), SNDR(@1.9531k) | 49.87 dB 39.38 dB | 69.59 dB 60.19 dB |
ENOB(@1.9531k) | 6.25 bit | 9.72 bit |
DNL(max) | +15.90/−15.36 LSB | +0.31/−0.11 LSB |
INL(max) | +1.78/−15.76 LSB | +0.25/−0.51 LSB |
Reference | [10] | [12] | [14] | [15] | [18] | This Work |
---|---|---|---|---|---|---|
Technology | 0.18-μm | 0.18-μm | 0.18-μm | 0.35-μm | 0.25-μm | 0.13-μm |
Architecture | SAR | Cyclic | Single Slope | Two-step SS | Multiple-ramp SS | SS With TDC |
Resolution/bit | 8 | 13 | 12 | 10 | 10 | 10 |
Conversion time/μs | 1.2 | 6.4 | 9.5 | 4 | 16 | 0.5 |
Power/μW | 209 | 450 * | 166.7 * | 150 | 91 | 355 |
FOM/fJ/step | 983.6 | 442.6 | 385.9 | 585.9 | 1138 | 211 |
Technology Photodiode Size | 0.13 μm 1P3M 25 μm × 100 μm |
---|---|
Supply Voltage | 3.3 V/1.5 V |
Line Rate | 2 M |
Sensitivity | 2.5 V/pA·s (max); 0.025 V/pA·s (min) |
Noise Floor | 0.7 mV |
Dynamic Range | 99.02 dB |
ADC resolution | 10 bit |
ADC ENOB | 9.72 bit (with calibration); 7.31 bit (without calibration) |
Power Consumption | 1048 μW/column |
5. Conclusions
Acknowledgments
Author Contributions
Conflicts of Interest
References
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Gao, Z.; Yang, C.; Xu, J.; Nie, K. A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors. Sensors 2015, 15, 28224-28243. https://doi.org/10.3390/s151128224
Gao Z, Yang C, Xu J, Nie K. A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors. Sensors. 2015; 15(11):28224-28243. https://doi.org/10.3390/s151128224
Chicago/Turabian StyleGao, Zhiyuan, Congjie Yang, Jiangtao Xu, and Kaiming Nie. 2015. "A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors" Sensors 15, no. 11: 28224-28243. https://doi.org/10.3390/s151128224