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Towards a verified compiler prototype for the synchronous language SIGNAL

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Abstract

SIGNAL belongs to the synchronous languages family which are widely used in the design of safety-critical real-time systems such as avionics, space systems, and nuclear power plants. This paper reports a compiler prototype for SIGNAL. Compared with the existing SIGNAL compiler, we propose a new intermediate representation (named S-CGA, a variant of clocked guarded actions), to integrate more synchronous programs into our compiler prototype in the future. The front-end of the compiler, i.e., the translation from SIGNAL to S-CGA, is presented. As well, the proof of semantics preservation is mechanized in the theorem prover Coq. Moreover, we present the back-end of the compiler, including sequential code generation and multithreaded code generation with time-predictable properties. With the rising importance of multi-core processors in safety-critical embedded systems or cyber-physical systems (CPS), there is a growing need for model-driven generation of multithreaded code and thus mapping on multi-core. We propose a time-predictable multi-core architecture model in architecture analysis and design language (AADL), and map the multi-threaded code to this model.

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Author information

Authors and Affiliations

  1. College of Computer Science and Technology, Nanjing University of Aeronautics and Astronautics, Nanjing, 210016, China

    Zhibin Yang

  2. IRIT-CNRS, Université de Toulouse, Toulouse, 31062, France

    Zhibin Yang, Jean-Paul Bodeveix & Mamoun Filali

  3. State Key Laboratory of Software Development Environment, Beihang University, Beijing, 100191, China

    Zhibin Yang, Kai Hu, Yongwang Zhao & Dianfu Ma

Authors
  1. Zhibin Yang
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  2. Jean-Paul Bodeveix
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  3. Mamoun Filali
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  4. Kai Hu
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  5. Yongwang Zhao
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  6. Dianfu Ma
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Corresponding author

Correspondence to Kai Hu.

Additional information

Zhibin Yang is an assistant professor at Nanjing University of Aeronautics and Astronautics, China. He received his PhD degree in computer science from Beihang University, China in 2012. From 2012 to 2014, he was a Postdoc in IRIT of University of Toulouse, France. His research interests include safety-critical real-time system, formal verification, AADL, and synchronous languages.

Jean-Paul Bodeveix received his PhD in computer science from University of Paris-Sud 11, France in 1989. He has been an assistant professor at University of Toulouse III, France since 1989, and is a professor in computer science since 2003. His main research interests concern formal specifications, automated and assisted verification of protocols as well as of proof environments. He has participated in European and national projects related to these domains. His current activities are linked to real time modeling and verification either via model checking techniques or at the semantics level.

Mamoun Filali is a full time researcher at Centre National de la Recherche Scientifique (CNRS), France. His main research interests concern the certified development of embedded systems, formal methods, model checking and theorem proving. During the last years, he has been mainly involved in the French nationwide TOPCASED project where he was concerned by the verification topic. He has also participated in the proposal of the AADL behavioral annex which has been adopted as part of the AADL SAE standard.

Kai Hu is an associate professor in Beihang University (BUAA), China. He received his PhD from Beihang University in 2001. From 2001 to 2004, he did his post-doctoral research at Nanyang Technological University, Singapore. Since 2004, he is the leader of the team of LDMC in the Institute of Computer Architecture (ICA), BUAA. His research interests concern embedded real time systems and high performance computing.

Yongwang Zhao is an assistant professor at Beihang University (BUAA), China. He received his PhD degree in computer science from BUAA in 2009. His research interests include formal methods, real-time operating systems, and AADL.

Dianfu Ma is a professor at Beihang University, China. He was the executive director of Chinese Computer Federation, the secretary of the steering committee of Computer Science and Technology Education in Ministry of Education of China. He is the vice director of SOA standards working group under the steering committee of China National Information Technology Standardization. He took charge of the National Basic Research Program (also called 973 Program), National High-tech 863 Program, National Natural Science Foundation of China, Key Technologies Research and Development Program, etc. He has published more than 50 academic papers in international journals or conferences. He received the 3rd prize of Science and Technology Innovation Award from Ministry of Education of China in 2003, and 1st prize of Science and Technology Innovation Award of Beijing in 2011. His research interesting includes services computing, real-time systems, and high dependable software.

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Yang, Z., Bodeveix, JP., Filali, M. et al. Towards a verified compiler prototype for the synchronous language SIGNAL. Front. Comput. Sci. 10, 37–53 (2016). https://doi.org/10.1007/s11704-015-4364-y

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