[go: up one dir, main page]
Skip to main content

Advertisement

Springer Nature Link
Log in

A ROM-less DDFS Based on a Parabolic Polynomial Interpolation Method with an Offset

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

A novel direct digital frequency synthesizer (DDFS) based on a parabolic polynomial with an offset is proposed in this paper. A 16-segment parabolic polynomial interpolation is adopted to replace the traditional ROM-based phase-to-amplitude conversion methods. Besides, the proposed parabolic polynomial interpolation is realized in a multiplier-less structure such that the speed can be significantly improved. This work is manufactured by a standard 0.13 μm CMOS cell-based technology. The maximum clock rate is 161 MHz, the core area is 0.33 mm2, and the spurious free dynamic range (SDRF) is 117 dBc by physical measurements on silicon.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10

Similar content being viewed by others

References

  1. Dosho, S., Yanagisawa, N., & Toyama, M. (2004). A design of compact PLL with adaptive active loop filter circuit. IEICE Transactions on Electronics, E87-C(6), 949–955.

    Google Scholar 

  2. Dosho, S., Yanagisawa, N., Sogawa, K., Yamada, Y., & Morie, T. (2007). An ultra-wide range digitally adaptive control phase locked loop with new 3-phase switched capacitor loop filter. IEICE Transactions on Electronics, 106(206), 93–98.

    Google Scholar 

  3. Kesoulis, M., Soudris, D., Koukourlis, C., & Thanailakis, A. (2007). Systematic methodology for designing low power direct digital frequency synthesizers. IET Circuits, Devices & Systems, 1(4), 293–304.

    Article  Google Scholar 

  4. Ashrafi, A., & Adhami, R. (2005). A direct digital frequency synthesizer utilizing quasi-linear interpolation method. In Proc. of 37th IEEE southeastern symposium on system theory (pp. 144–148).

  5. Ashrafi, A., & Adhami, R. (2006). An optimized direct digital frequency synthesizer based on even fourth order polynomial interpolation. In Proc. of 38th IEEE southeastern symposium on system theory (pp. 109–113).

  6. Jafari, H., Ayatollahi, A., & Mirzakuchaki, S. (2005). A low power, high SFDR, ROM-less direct digital frequency synthesize. In 2005 IEEE conf. on electron devices and solid-state circuits (pp. 50–54).

  7. De Caro, D., & Strollo, A. G. M. (2005). High-performance direct digital frequency synthesizers in 0.25 μm CMOS using dual-slope approximation. IEEE Journal of Solid-State Circuits, 40(11), 2220–2227.

    Article  Google Scholar 

  8. Song, Y., & Kim, B. (2003). A 250 MHz direct digital frequency synthesizer with delta-sigma noise shaping. In 2003 IEEE int. solid-state circuits conf. (ISSCC 2003) (Vol. 1, pp. 472–509).

  9. Nicholas, H. T., & Samueli, H. (1987). An analysis of the output spectrum of direct digital frequency synthesizers in the presence of phase-accumulator truncation. In 41st annual frequency control symposium (pp. 495–502).

  10. Yu, X., Dai, F. F., Shi, Y., & Zhu, R. (2005). 2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer. In IEEE inter. symp. on circuits and systems (Vol. 5, pp. 4397–4400).

  11. Yi, S. C., Lee, K. T., Chen, J. J., & Lin, C. H. (2006). A low-power efficient direct digital frequency synthesizer based on new two-level lookup table. In 2006 Canadian conference on electrical and computer engineering (pp. 963–966).

  12. Kesoulis, M., Soudris, D., Koukourlis, C., & Thanailakis, A. (2007). Systematic methodology for designing low power direct digital frequency synthesizers. IET Circuits, Devices & Systems, 1(4), 293–304.

    Article  Google Scholar 

  13. Jeng, S. S., Lin, H. C., & Wu, C. Y. (2008). DDFS design using the equi-section division method for SDR transceiver. In IEEE 19th international symposium on personal, indoor and mobile radio communications (pp. 1–5).

  14. Li, X., Lai, L., Lei, A., & Lai, Z. (2008). A memory-reduced direct digital frequency synthesizer for OFDM receiver systems. IEEE Transactions on Consumer Electronics, 54(4), 1564–1568.

    Article  Google Scholar 

Download references

Acknowledgements

This investigation is partially supported by National Science Council under grant NSC 96-2628-E-110-019-MY3, and National Health Research Institutes under grant NHRI-EX99-9732EI. It is also partially supported by Ministry of Economic Affairs, Taiwan, under grant 98-EC-17-A-01-S1-104, 98-EC-17-A-02-S2-0017, 98-EC-17-A-19-S1-133 and 98-EC-17-A-07-S2-0010. The authors would like to express their deepest gratefulness to Chip Implementation Center of National Applied Research Laboratories, Taiwan, for their thoughtful chip fabrication service.

Author information

Authors and Affiliations

  1. Department of Electrical Engineering, National Sun Yat-Sen University, 70 Lian-Hai Rd., Kaohsiung, Taiwan

    Chua-Chin Wang, Chia-Hao Hsu, Chia-Chuan Lee & Jian-Ming Huang

Authors
  1. Chua-Chin Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Chia-Hao Hsu
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Chia-Chuan Lee
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Jian-Ming Huang
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Chua-Chin Wang.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Wang, CC., Hsu, CH., Lee, CC. et al. A ROM-less DDFS Based on a Parabolic Polynomial Interpolation Method with an Offset. J Sign Process Syst 64, 351–359 (2011). https://doi.org/10.1007/s11265-010-0498-1

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-010-0498-1

Keywords