Abstract
To tolerate Double Nodes Upset (DNU) and Triple Nodes Upset (TNU), we propose the DNU Tolerant Latch (DNUL) and TNU Tolerant Latch (TNUL) with low overhead and high stability. Both DNUL and TNUL are composed of the looped Input-Split C-Elements (ISCs) and the C-Elements (CEs) at the output level. Based on the robust blocking ability of the ISCs, the simultaneous upset of all inputs of the CE can be blocked. DNUL and TNUL have low overhead with fewer transistors by utilizing the clock-gating and high-speed path technique. Exhaustive HSPICE simulation shows that, in contrast to previous DNU tolerant latches, DNUL is optimal in terms of delay, power consumption and product of delay and power (PDP), but is suboptimal in terms of area overhead. Compared with all alternative structures, TNUL is the best in terms of delay and PDP. Compared to other TNU tolerant latches, TNUL achieves a suboptimal power consumption and area overhead. Variation analysis shows that DNUL and TNUL are insensitive to variations of process, voltage and temperature (PVT).
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Data Availability
The datasets generated and analyzed during the current study are available from the corresponding author on reasonable request.
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This work was supported in part by National Natural Science Foundation of China under grant nos. 62274052, 61834006, 62027815, 61874157.
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Huang, Z., Wang, H., Ma, D. et al. Low Overhead and High Stability Radiation-Hardened Latch for Double/Triple Node Upsets. J Electron Test 39, 289–301 (2023). https://doi.org/10.1007/s10836-023-06064-9
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DOI: https://doi.org/10.1007/s10836-023-06064-9