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Genetic algorithm for test pattern generator design

Automatic evolution of circuits

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Abstract

The paper describes an approach for the generation of a deterministic test pattern generator logic, which is composed of D-type and T-type flip-flops. This approach employs a genetic algorithm that searches for an acceptable practical solution in a large space of possible implementations. In contrast to conventional approaches the proposed one reduces the gate count of a built-in self-test structure by concurrent optimization of multiple parameters that influence the final solution. The optimization includes the search for: the optimal combination of register cells type; the presence of inverters at inputs and outputs; the test patterns order in the generated test sequence; and the bit order of test patterns. Results of benchmark experiments and comparison with similar studies demonstrate the efficiency of the proposed evolutionary approach.

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Authors and Affiliations

  1. Institute of Electronics, Silesian University of Technology, 44100, Gliwice, Poland

    Tomasz Garbolino

  2. Computer Systems Department, Jožef Stefan Institute, 1000, Ljubljana, Slovenia

    Gregor Papa

Authors
  1. Tomasz Garbolino
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  2. Gregor Papa
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Correspondence to Gregor Papa.

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Garbolino, T., Papa, G. Genetic algorithm for test pattern generator design. Appl Intell 32, 193–204 (2010). https://doi.org/10.1007/s10489-010-0214-7

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