[go: up one dir, main page]
Skip to main content
Springer Nature Link
Log in

Strategies for design automation of high speed digital filters

  • Published:
Journal of VLSI signal processing systems for signal, image and video technology Aims and scope Submit manuscript

Abstract

Optimization techniques for DSP circuits are described based on the design experience with a number of high-speed digital filter chips. These designs show that efficient high speed digital filter designs can be achieved using several optimizations at the architecture, circuit, and layout level. The problems of automating these optimizations in a general DSP synthesis environment are discussed, and possible CAD solutions are proposed.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. M. Hatamian and S. Rao, “A 100 MHz 40-tap programmable FIR filter chip,”Proc. IEEE Int. Symp. Circuits and Systems, 1990, pp. 3053–3056.

  2. T. Lin and H. Samueli, “A 200-MHz CMOSx/sin(x) Digital Filter for Compensating D/A Converter Frequency Response Distortion,”IEEE J. Solid-State Circuits, vol. 26, pp. 1278–1285, Sept. 1991.

    Article  Google Scholar 

  3. F. Lu and H. Samueli, “A Reconfigurable Decision-Feedback Equalizer Chip Set Architecture for High Bit-Rate QAM Digital Modems,”Proc. ICASSP 1991, pp. 1185–1188.

  4. T. Noll and S. Meier, “A 40 MHz programmable semi-systolic transversal filter,”ISSCC Digest of Technical Papers, Feb. 1986, pp. 180–181.

  5. B. Wong and H. Samueli, “A 200-MHz All-Digital QAM Modulator and Demodulator in 1.2μm CMOS for Digital Radio Applications,”IEEE Journal of Solid-State Circuits, vol. 26, pp. 1970–1979, Dec. 1991.

    Article  Google Scholar 

  6. K. Parhi and M. Hatamian, “A High Sample Rate Digital Filter Chip,”VLSI Signal Processing II, IEEE Press, 1988, pp. 3–14.

  7. S. Hang and R. Jain, “Decimation Filter Compiler for Oversampling A/D Applications,”Proc. ICASSP 1992.

  8. R. Hawley, T. Lin and H. Samueli, “A 200-MHz Double-Sideband to Single-Sideband Converter in 1-μm CMOS Generated by Silicon Compiler,”VLSI Circuits Symposium, June 1992, pp. 72–73.

  9. P. Jain, R. Yang and T. Yoshino, “FIRGEN: A Computer-Aided Design System for High Performance FIR Integrated Circuits,”IEEE Trans. on Signal Processing, vol. 39, no. 7, pp. 1655–1658.

  10. J. Laskowski and H. Samueli, “A 150-MHz 43-tap Half-Band FIR Digital Filter in 1.2-μm CMOS Generated by Silicon Compiler,”Proc. Custom Integrated Circuits Conference, 1992.

  11. L. Liu, R. Jain and T. Yoshino, “A 23.8 MHz 73-dB Attenuation Recursive Digital Filter IC,”IEEE Custom Integrated Circuits Conference, May 1992.

  12. R. Brayton et al., Logic Minimization Algorithms for VLSI Synthesis, Boston, Kluwer Academic, 1984.

    Book  MATH  Google Scholar 

  13. R. Brayton et al, “MIS: A multiple-level logic optimization system,”IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 1062–1081, Nov, 1987.

    Article  Google Scholar 

  14. L. Lavagno et al., “MIS-MV: Optimization of multi-level logic with multiple-valued inputs,”Proc. Int. Conf. Computer-Aided Design, Nov. 1990, pp. 560–563.

  15. A. R. Newton, “Techniques for logic synthesis,”VLSI Design of Digital Systems, Proc. IFIP TC 10/WG 10.5 Int. Conf. on Very large Scale Integration. (Tokyo, Japan, 1985), E. Horbst, Ed. Amsterdam, The Netherlands: North Holland, 1986.

    Google Scholar 

  16. R. Rudell and A. Sangiovanni-Vincentelli, “ESPRESSO-MV: Algorithms for multiple-valued logic minimization,”Proc. 1985 Custom Integrated Circuits Conf., Portland, OR, May 1985.

  17. J. Rabaey et al., “CATHEDRAL-II: A Synthesis System for Multiprocessor DSP Systems,”Silicon Compilation, Addison-Wesley, Dec. 1987.

  18. A Parker et al., “MAHA: A Program for Datapath Synthesis,”Proc. 23rd Design Automation Conference, June, 1986.

  19. N. Park and A. Parker, “Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications,”IEEE Trans. Computer Aided Design, vol. CAD-7, Mar, 1988.

  20. C. Chu et al., “HYPER: An Interactive Synthesis Environment for High Performance Real Time Applications,”Proc. IEEE ICCD Conf., Nov. 1989.

  21. B. Haroun and M. Elmasry, “Architectural Synthesis for DSP Silicon Compilers,”IEEE Trans. on CAD, vol. 8, pp. 431–447, 1989.

    Article  Google Scholar 

  22. P. Duncan et al., “Hi-PASS: A Computer-Aided Synthesis System for Maximally Parallel Digital Signal Processing ASICs,”Proc. ICASSP 1992, pp. 605–608.

  23. J. Darringer et al., “Logic Synthesis through Local Transformations,”IBM Jour. of Research and Development, July 1981.

  24. A de Geus and W. Cohen, “A Rule-Based System for Optimizing Combinational Logic,”IEEE Design and Test of Computers, August 1985.

  25. R. Jain et al., “Custom Design of a VLSI 10 PCM-FDM Transmultiplier from System Specifications to Circuit Layout Using a Computer-Aided Design System,”Jour. Solid-State Circuits, vol. SC-21, no. 1, pp. 73–85.

  26. M. Potkonjak and J. Rabaey, “Optimizing Resource Utilization Using Transformations,”IEEE ICCAD-91.

  27. J. Laskowski,A Silicon Compiler for Linear-Phase FIR Digital Filters, M.S. Thesis, UCLA 1991.

  28. C. E. Leiserson and J. Saxe, “Retiming Synchronous Circuitry,”Algorithmica, vol. 6, no. 1, pp. 5–35, 1991.

    Article  MathSciNet  MATH  Google Scholar 

  29. S. Note et al., “Combined Hardware Selection and Pipelining in High Performance Data-Path Design,”Proc. IEEE ICCD, Sept. 1990.

  30. M. Potkonjak and J. Rabaey, “Retiming for Scheduling,”VLSI Signal Processing IV, 1990.

  31. K. Kindsfater, “Computer-Aided Design of High Data-Rate QAM Modem Circuits,” submitted toIEEE International Conf. on Communications, May 1993.

  32. C. Sechen and A. Sangiovanni-Vincentelli, “The TimberWolf Placement and Routing Package,”IEEE Jour. of Solid State Circuits, April 1985.

  33. C. Sechen, “Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing,”Proc. 25th Design Automation Conf., 1988, pp. 73–80.

  34. S. Kirkpatrick et al., “Optimization by Simulated Annealing,” Science, vol. 220, no. 4598, pp. 671–680, 1983.

    Article  MathSciNet  MATH  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. UCLA Electrical Engineering, 56-147 Engineering IV, 90024, Los Angeles, California, USA

    Phillip Duncan, Ken Kindsfater, Lynette Liu & Rajeev Jain

Authors
  1. Phillip Duncan
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Ken Kindsfater
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Lynette Liu
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Rajeev Jain
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Duncan, P., Kindsfater, K., Liu, L. et al. Strategies for design automation of high speed digital filters. Journal of VLSI Signal Processing 9, 105–119 (1995). https://doi.org/10.1007/BF02406473

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF02406473

Keywords

Search

Navigation