Abstract
A Convolutional Neural Network represents a machine learning model commonly employed for pattern recognition and classification tasks in image and video-based applications. The architecture of a Convolutional Neural Network typically comprises a sequence of convolutional layers paired with pooling layers, with the final output being classified by a fully connected layer. The role of the convolutional layer is to enable the mapping of distinctive image features, while the pooling layer serves to reduce the dimensionality of matrices and simplify the data. In this research endeavor, we delve into assessing the performance of a parallelized implementation of a Convolutional Neural Network executed on a Multiprocessor System-on-Chip.
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Acknowledgment
The authors are grateful to FAPERJ (Fundação de Amparo á Pesquisa do Estado do Rio de janeiro, http://www.faperj.br), CNPq (Conselho Nacional de Desenvolvimento Científico e Tecnológico, http://www.cnpq.br) and CAPES (Coordenação de Aperfeiçoamento de Pessoal de Níível Superior, http://www.capes.gov.br/) for their continuous financial support.
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de Macedo Mourelle, L., Nedjah, N., Cardoso, A.N. (2024). Parallel Implementation of a Convolutional Neural Network on an MPSoC. In: Fujita, H., Cimler, R., Hernandez-Matamoros, A., Ali, M. (eds) Advances and Trends in Artificial Intelligence. Theory and Applications. IEA/AIE 2024. Lecture Notes in Computer Science(), vol 14748. Springer, Singapore. https://doi.org/10.1007/978-981-97-4677-4_28
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DOI: https://doi.org/10.1007/978-981-97-4677-4_28
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