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RRAM Cross-Point Arrays

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3D Flash Memories

Abstract

In the age of Big Data, it has been always a dream for researchers to find the next generation nonvolatile memory with higher density, lower latency and lower cost. As a matter of fact, the last mainstream memory, NAND Flash memory, was created decades ago. Nowadays, NAND Flash memory, based on metal-oxide-semiconductor field-effect-transistor with an additional floating gate, is still one of the most popular nonvolatile memories. However, its speed and density are now approaching the physical limits of its basic structure. It takes longer than 1μsec to store electrons into the floating gate (Lee et al. in Two series oxide resistors applicable to high speed and high density nonvolatile memory. Adv Mater 19(22):3919–3923, 2007, [1]), and it seems impossible to scale planar technologies below 10 nm. This is not only due to the cost of lithography, but also to the crosstalk and parasitic effects caused by the thick gate. In fact, to make sure that electrons don’t leak away from the floating gate, gate thickness can’t be too thin. Moreover, since the number of electrons trapped inside the floating gate is less than 100 at 20 nm, losing few electrons can cause severe reliability issues (Sung and Hagop in Next generation nonvolatile memory, its impact on computer system (Resources of Crossbar Company), [2]).

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References

  1. M.-J. Lee et al., Two series oxide resistors applicable to high speed and high density nonvolatile memory. Adv. Mater. 19(22), 3919–3923 (2007)

    Article  Google Scholar 

  2. H.J. Sung, N. Hagop, in Next Generation Nonvolatile Memory, Its Impact on Computer System (Resources of Crossbar Company, 2013)

    Google Scholar 

  3. B.J. Choi et al., in Electrical performance and scalability of Pt dispersed SiO2 nanometallic resistance switch. Nano Lett. 13(7), 3213–3217 (2013)

    Google Scholar 

  4. T. Yanagida et al., in Scaling effect on unipolar and bipolar resistive switching of metal oxides. Sci. Rep. 3 (2013)

    Google Scholar 

  5. C. Ho et al., 9 nm half-pitch functional resistive memory cell with < 1µA programming current using thermally oxidized sub-stoichiometric WOx film, in 2010 International Electron Devices Meeting (2010)

    Google Scholar 

  6. H.-S.P. Wong et al., Metal–oxide RRAM. Proc. IEEE 100(6), 1951–1970 (2012)

    Article  Google Scholar 

  7. H. Ohno et al., Magnetic tunnel junction for nonvolatile CMOS logic, in Electron Devices Meeting (IEDM), 2010 IEEE International. IEEE (2010)

    Google Scholar 

  8. Y. Watanabe et al., Current-driven insulator–conductor transition and nonvolatile memory in chromium-doped SrTiO3 single crystals. Appl. Phys. Lett. 78(23), 3738–3740 (2001)

    Article  Google Scholar 

  9. C. Rohde et al., Identification of a determining parameter for resistive switching of TiO2 thin films. Appl. Phys. Lett. 86(26), 262907 (2005)

    Google Scholar 

  10. L.P. Ma, J. Liu, Y. Yang, Organic electrical bistable devices and rewritable memory cells. Appl. Phys. Lett. 80(16), 2997–2999 (2002)

    Article  Google Scholar 

  11. I.G. Baek et al., Highly scalable nonvolatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses, in Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International (2004)

    Google Scholar 

  12. H.Y. Lee et al., Evidence and solution of over-RESET problem for HfO x based resistive memory with sub-ns switching speed and high endurance, in Electron Devices Meeting (IEDM), 2010 IEEE International. IEEE (2010)

    Google Scholar 

  13. B. Govoreanu et al., 10 × 10 nm 2 Hf/HfO x crossbar resistive RAM with excellent performance, reliability and low-energy operation, in Electron Devices Meeting (IEDM), 2011 IEEE International. IEEE (2011)

    Google Scholar 

  14. M.-J. Lee et al., in A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5−x/TaO2−x bilayer structures. Nat. Mater. 10(8), 625–630 (2011)

    Google Scholar 

  15. F. Pan et al., Recent progress in resistive random access memories: Materials, switching mechanisms, and performance. Mater. Sci. Eng. R Rep. 83(9), 1–59 (2014)

    Article  Google Scholar 

  16. H.S. Philip Wong et al., Phase change memory. Proc. IEEE 98(12), 2201–2227 (2010)

    Article  Google Scholar 

  17. I.G. Baek et al., Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage application, in Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International. IEEE (2005)

    Google Scholar 

  18. M.-J. Lee et al., 2-stack 1D-1R cross-point structure with oxide diodes as switch elements for high density resistance RAM applications, in Electron Devices Meeting, 2007. IEDM 2007. IEEE International. IEEE (2007)

    Google Scholar 

  19. Y. Bai et al., in Study of multi-level characteristics for 3D vertical resistive switching memory. Sci. Rep. 4 (2014)

    Google Scholar 

  20. S. Yu et al., HfOx-based vertical resistive switching random access memory suitable for bit-cost-effective three-dimensional cross-point architecture. ACS Nano 7(3), 2320–2325 (2013)

    Google Scholar 

  21. W.C. Chien et al., Multi-layer sidewall WOx resistive memory suitable for 3D ReRAM, in 2012 Symposium on VLSI Technology (VLSIT). IEEE (2012)

    Google Scholar 

  22. J.-Y. Seok et al., A review of three-dimensional resistive switching cross-bar array memories from the integration and materials property points of view. Adv. Funct. Mater. 24(34), 5316–5339 (2014)

    Google Scholar 

  23. C.-W. Hsu et al., Self-rectifying bipolar TaOx/TiO2 RRAM with superior endurance over 10 12 cycles for 3D high-density storage-class memory, in 2013 Symposium on VLSI Technology (VLSIT). IEEE (2013)

    Google Scholar 

  24. K.-S. Li et al., Utilizing Sub-5 nm sidewall electrode technology for atomic-scale resistive memory fabrication, in 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers. IEEE (2014)

    Google Scholar 

  25. Y. Bai et al., in Stacked 3D RRAM array with graphene/CNT as edge electrodes. Sci. Rep. 5 (2015)

    Google Scholar 

  26. I.G. Baek et al., Realization of vertical resistive memory (VRRAM) using cost effective 3D process, in Electron Devices Meeting (IEDM), 2011 IEEE International. IEEE (2011)

    Google Scholar 

  27. S.G. Park et al., A non-linear ReRAM cell with sub-1μA ultralow operating current for high density vertical resistive memory (VRRAM), in Electron Devices Meeting, 1988. IEDM ‘88. Technical Digest, pp. 20.8.1–20.8.4 (2012)

    Google Scholar 

  28. H.S. Yoon et al., Vertical cross-point resistance change memory for ultra-high density non-volatile memory applications, in 2009 Symposium on VLSI Technology (2009)

    Google Scholar 

  29. Y. Deng et al., Design and optimization methodology for 3D RRAM arrays, in Electron Devices Meeting (IEDM), 2013 IEEE International. IEEE (2013)

    Google Scholar 

  30. H.-Y. Chen et al., HfOx based vertical resistive random access memory for cost-effective 3D cross-point architecture without cell selector, in Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE (2012)

    Google Scholar 

  31. E. Cha et al., Nanoscale (∼ 10 nm) 3D vertical ReRAM and NbO 2 threshold selector with TiN electrode, in Electron Devices Meeting (IEDM), 2013 IEEE International. IEEE (2013)

    Google Scholar 

  32. C.-W. Hsu et al., 3D vertical TaO x/TiO 2 RRAM with over 10 3 self-rectifying ratio and sub-μA operating current, in 2013 IEEE International Electron Devices Meeting (2013)

    Google Scholar 

  33. A. Chen, Nonlinearity and Asymmetry for Device Selection in Cross-Bar Memory Arrays (2015)

    Google Scholar 

  34. A. Flocke, G.N. Tobias, Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory, in 33rd European Conference on Solid State Circuits (ESSCIRC 2007). IEEE (2007)

    Google Scholar 

  35. C.-L. Lo et al., in Dependence of read margin on pull-up schemes in high-density one selector–one resistor crossbar array. IEEE Trans. Electr. Devices 60(1), 420–426 (2013)

    Google Scholar 

  36. J.-J. Huang et al., One selector-one resistor (1S1R) crossbar array for high-density flexible memory applications, in Electron Devices Meeting (IEDM), 2011 IEEE International. IEEE (2011)

    Google Scholar 

  37. P. Sun et al., in Physical model of dynamic Joule heating effect for reset process in conductive-bridge random access memory. J. Comput. Electr. 13(2), 432–438 (2014)

    Google Scholar 

  38. P. Sun et al., in Thermal crosstalk in 3-dimensional RRAM crossbar array. Sci. Rep. 5 (2015)

    Google Scholar 

  39. X.P. Wang et al., Highly compact 1T-1R architecture (4F 2 footprint) involving fully CMOS compatible vertical GAA nano-pillar transistors and oxide-based RRAM cells exhibiting excellent NVM properties and ultra-low power operation, in Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE (2012)

    Google Scholar 

  40. C.-H. Wang et al., Three-dimensional 4F 2 ReRAM cell with CMOS logic compatible process, in Electron Devices Meeting (IEDM), 2010 IEEE International. IEEE (2010)

    Google Scholar 

  41. G. Tallarida et al., Low temperature rectifying junctions for crossbar non-volatile memory devices, in 2009 IEEE International Memory Workshop (2009)

    Google Scholar 

  42. L. Zhang et al. High-drive current (>1MA/cm 2) and highly nonlinear (>10 3) TiN/amorphous-Silicon/TiN scalable bidirectional selector with excellent reliability and its variability impact on the 1S1R array performance, in Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE (2014)

    Google Scholar 

  43. W. Lee et al., Varistor-type bidirectional switch (J MAX > 10 7 A/cm 2, selectivity ∼ 10 4) for 3D bipolar resistive memory arrays, in 2012 Symposium on VLSI Technology (VLSIT). IEEE (2012)

    Google Scholar 

  44. D. Lee et al., BEOL compatible (300 °C) TiN/TiO x/Ta/TiN 3D nanoscale (∼10 nm) IMT selector, in Electron Devices Meeting (IEDM), 2013 IEEE International. IEEE (2013)

    Google Scholar 

  45. S.H. Jo et al., 3D-stackable crossbar resistive memory based on field assisted superlinear threshold (FAST) selector, in Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE (2014)

    Google Scholar 

  46. M.-J. Lee et al., Highly-scalable threshold switching select device based on chaclogenide glasses for 3D nanoscaled memory arrays, in Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE (2012)

    Google Scholar 

  47. H. Yang et al., Novel selector for high density non-volatile memory with ultra-low holding voltage and 10 7 on/off ratio, in 2015 Symposium on VLSI Technology (VLSI Technology). IEEE (2015)

    Google Scholar 

  48. S. Kim et al., Performance of threshold switching in chalcogenide glass for 3D stackable selector, in Proceedings of Symposium on VLSIT (2013)

    Google Scholar 

  49. I. Riess, Mixed ionic–electronic conductors—material properties and applications. Solid State Ionics 157(1), 1–17 (2003)

    Article  Google Scholar 

  50. K. Virwani et al., in Sub-30 nm scaling and high-speed operation of fully-confined access-devices for 3D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC) materials. IEDM Tech. Dig. 36–39 (2012)

    Google Scholar 

  51. K. Gopalakrishnan et al., Highly-scalable novel access device based on mixed ionic electronic conduction (MIEC) materials for high density phase change memory (PCM) arrays, in 2010 Symposium on VLSI Technology (VLSIT). IEEE (2010)

    Google Scholar 

  52. G. Burr et al., Recovery dynamics and fast (sub-50 ns) read operation with access devices for 3D crosspoint memory based on mixed-ionic-electronic-conduction (MIEC), in 2013 Symposium on VLSI Technology (VLSIT). IEEE (2013)

    Google Scholar 

  53. X.A. Tran et al., Self-rectifying and forming-free unipolar HfOx based-high performance RRAM built by fab-avaialbe materials, in Electron Devices Meeting, 1988. IEDM ‘88. Technical Digest, pp. 31.2.1–31.2.4 (2011)

    Google Scholar 

  54. B. Govoreanu et al., Vacancy-modulated conductive oxide resistive RAM (VMCO-RRAM): An area-scalable switching current, self-compliant, highly nonlinear and wide on/off-window resistive switching cell, in Electron Devices Meeting (IEDM), 2013 IEEE International. IEEE (2013)

    Google Scholar 

  55. S. Lee et al., Selector-less ReRAM with an excellent non-linearity and reliability by the band-gap engineered multi-layer titanium oxide and triangular shaped AC pulse, in Electron Devices Meeting (IEDM), 2013 IEEE International. IEEE (2013)

    Google Scholar 

  56. E. Linn et al., in Complementary resistive switches for passive nanocrossbar memories. Nat. Mater, 9(5), 403–406 (2010)

    Google Scholar 

  57. R. Rosezin et al., Integrated complementary resistive switches for passive high-density nanocrossbar arrays. Elect. Device Lett. 32(2), 191–193 (2011)

    Article  Google Scholar 

  58. F. Nardi et al., Complementary switching in metal oxides: Toward diode-less crossbar RRAMs, in Electron Devices Meeting (IEDM), 2011 IEEE International. IEEE (2011)

    Google Scholar 

  59. S. Yu et al., 3d vertical rram-scaling limit analysis and demonstration of 3d array operation, in 2013 Symposium on VLSI Technology (VLSIT). IEEE (2013)

    Google Scholar 

  60. The information Intel pronounced at IDF 15. http://www.eetimes.com/document.asp?doc_id=1327289

  61. R. Fackenthal et al., 19.7 A 16 Gb ReRAM with 200 MB/s write and 1 GB/s read in 27 nm technology. Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International. IEEE (2014)

    Google Scholar 

  62. T.-Y. Liu et al., A 130.7 mm 2 2-layer 32 Gb ReRAM memory device in 24 nm technology, in Digest of Technical Papers—IEEE International Solid-State Circuits Conference, pp. 210–211 (2013)

    Google Scholar 

  63. T.-Y. Liu et al., in A 130.7-2-layer 32-Gb ReRAM memory device in 24-nm technology. IEEE J. Solid-State Circ. 49(1), 140–153 (2014)

    Google Scholar 

  64. S.H. Jo et al., in Cross-point resistive ram based on field-assisted superlinear threshold selector. IEEE Trans. Elect. Devices (2015)

    Google Scholar 

  65. S.H. Jo et al., “Sneak path” breakthrough heralds arrival of ultra-high density resistive memory. Chip Des. (Winter 2015)

    Google Scholar 

  66. M.-C. Hsieh et al., Ultra high density 3D via RRAM in pure 28 nm CMOS process, in Electron Devices Meeting (IEDM), 2013 IEEE International. IEEE (2013)

    Google Scholar 

  67. Y.-W. Chin et al., Point twin-bit RRAM in 3D interweaved cross-point array by Cu BEOL process, in Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE (2014)

    Google Scholar 

  68. M.-J. Lee et al., in Electrical manipulation of nanofilaments in transition-metal oxides for resistance-based memory. Nano Lett. 9(4), 1476–1481 (2009)

    Google Scholar 

  69. H. Li et al., in A SPICE model of resistive random access memory for large-scale memory array simulation. Elect. Device Lett. 35(2), 211–213 (2014)

    Google Scholar 

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Author information

Authors and Affiliations

  1. Institute of Microelectronics, Tsinghua University, Beijing, China

    Huaqiang Wu, Yan Liao, Bin Gao & He Qian

  2. Micron Technology Inc., Boise, USA

    Debanjan Jana

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  1. Huaqiang Wu
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  2. Yan Liao
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  3. Bin Gao
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  4. Debanjan Jana
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  5. He Qian
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Corresponding author

Correspondence to Huaqiang Wu .

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Editors and Affiliations

  1. Microsemi Corporation, Performance Storage BU, Vimercate, Italy

    Rino Micheloni

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Wu, H., Liao, Y., Gao, B., Jana, D., Qian, H. (2016). RRAM Cross-Point Arrays. In: Micheloni, R. (eds) 3D Flash Memories. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7512-0_8

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  • DOI: https://doi.org/10.1007/978-94-017-7512-0_8

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