Abstract
DIMMnet-2 is a network interface for PC cluster, plugged into a DIMM slot. Connecting network interface into commonly used memory bus reduces the cost of building PC cluster compared with using expensive machines with recent high performance I/O bus like PCIX. Moreover, low latency communication from the host CPU can be achieved. In this paper, implementation of the mechanisms for low latency communication on the DIMMnet-2 prototype board by making the best use of the memory slot is shown. Its latency for 4 Bytes data transfer is only 1.4 μs which is lower than those of InfiniBand and QsNET II on condition those host processes are Intel Xeon.
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Miyabe, Y. et al. (2008). Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2. In: Labarta, J., Joe, K., Sato, T. (eds) High-Performance Computing. ISHPC ALPS 2005 2006. Lecture Notes in Computer Science, vol 4759. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-77704-5_18
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DOI: https://doi.org/10.1007/978-3-540-77704-5_18
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-77703-8
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