Abstract
Field-programmable gate arrays have the potential to provide reconfigurability in the presence of faults. In this paper, we have investigated the problem of partially reconfiguring FPGA mapped designs. We present a maximum matching based algorithm to reconfigure the placement on an FPGA with little or no impact on circuit performance. Experimental results indicate the algorithm works well for both fault tolerance and reconfigurable computing applications. We also present the motivation and feasibility of using a similar approach for dynamic circuit reconfigurability.
partially supported by contract number F33615-96-C-1912 from Wright Laboratories of the US Air Force
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Emmert, J.M., Bhatia, D. (1997). Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement. In: Luk, W., Cheung, P.Y.K., Glesner, M. (eds) Field-Programmable Logic and Applications. FPL 1997. Lecture Notes in Computer Science, vol 1304. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-63465-7_219
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DOI: https://doi.org/10.1007/3-540-63465-7_219
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