Abstract
With increasing FPGA device capacity and design sizes, physical design closure is becoming more difficult, usually requiring multiple lengthy cycles of placement and routing. Increasing demands are being placed upon the placement method to produce routable solutions. Existing FPGA physical design methodologies treat placement and routing as two distinct steps resulting in significant loss of quality and increased design times. A tighter integration between placement and routing is expected to reduce the overall physical design time and produce better quality solutions. This paper presents a new methodology for tightly integrated placement and routing for FPGAs. It provides the capability to introduce the routing concepts to the placement stage itself, ensuring the placement is routability driven and that desired good routes exist for all nets, in the routing stage. This methodology has been implemented for XC6200 family of FPGAs, but can be used with any FPGA architecture.
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Kannan, P., Bhatia, D. (2001). Tightly Integrated Placement and Routing for FPGAs. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_25
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DOI: https://doi.org/10.1007/3-540-44687-7_25
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