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ORCIDISOCC 2021: Jeju Island, South Korea
- 18th International SoC Design Conference, ISOCC 2021, Jeju Island, South Korea, Republic of, October 6-9, 2021. IEEE 2021, ISBN 978-1-6654-0174-6
- Jingying Zhang, Yang Zhao, Mingyi Chen, Chixiao Chen, Fan Ye, Liang Qi:
Self-coupled MASH Delta-Sigma Modulator with Zero Optimization. 1-2 - Dohyeon Lee, Heecheol Hwang, Hyunteck Oh, Yongchan James Ban:
Mitigating IR-Drop with Design Technology Co-Optimization for Sub-Nanometer Node Technology. 1-2 - Pang-Yen Lou, Yung-Yuan Ho, Chua-Chin Wang:
Analysis of Layout Arrangment for CMOS Oscillators to Reduce Overall Variation on Wafer. 1-2 - Youngkwang Lee, Donghyun Han, Sooryeong Lee, Sungho Kang:
A Circular-based TSV Repair Architecture. 1-2 - Jungyun Choi, Kyungsu Kang, Byunghoon Lee, Sangho Park, Jae-Woo Im:
Early HW/SW Co-Verification Using Virtual Platforms. 1-2 - Chinmaye Ramamurthy, Chetan D. Parikh, Subhajit Sen:
Digital Calibration of 1.5 bits/stage Algorithmic ADC. 3-4 - Jung-Hyun Lee, Kang-Yoon Lee:
A Design of Low-Power Bootstrapped CMOS Switch for 20MS/s 12-bit Charge Sharing SAR ADCs. 5-6 - Sang-Hoon Lee, Won-Young Lee:
A 0.6-V 400-KS/s Low Noise Asynchronous SAR ADC With Dual-Domain Comparison. 7-8 - Ziwei Li, Guoyao Wu, Yutong Zhao
, Fan Ye, Junyan Ren:
Resistive Degeneration Linearization Dynamic Residue Amplifiers for Pipelined ADCs. 9-10 - Pang-Yen Lou, Ying-Xuan Chen, Chua-Chin Wang:
On-chip CMOS Corner Detector Design for Panel Drivers. 11-12 - Heping Yang, Hui Chen, Yuxiang Fu, Li Li:
Low-Latency Architecture for Implementing Floating-Point Multiplier and Divider Based on Symmetric-Mapping LUT. 13-14 - Jin Xu, Lin Jiang, Hui Chen, Yuxiang Fu, Li Li:
A Low-Complexity Architecture for Implementing Square to Tenth Root of Complex Numbers. 15-16 - Ronaldo Serrano, Ckristian Duran, Trong-Thuc Hoang, Marco Sarmiento, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham:
ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3. 17-18 - Jae Hong Roh, Useok Lee, Yongje Lee, Myung Hoon Sunwoo:
Efficient Partial Sum Architecture and Memory Reduction Method for SC-Flip Polar Decoder. 19-20 - Joseph Chang, Truong Q. Nguyen:
Enhanced Depth Map Estimation in Low Light Conditions for RGB Cameras. 21-22 - Shiwei Jin, Ji Dai, Truong Q. Nguyen:
Differential Gaze Estimation with Ocular Counter-Rolling Compensation. 23-24 - Jin Hyun, Seungsik Moon, Youngjoo Lee:
Low-Complexity Voice Activity Detection Algorithm for Edge-Level Device. 25-26 - Chi-Jui Ho, Yiqian Wang, Junkang Zhang, Truong Q. Nguyen, Cheolhong An:
A Convolutional Neural Network Pipeline For Multi-Temporal Retinal Image Registration. 27-28 - Shubham Kumar, Jonathan Mi, Qingyuan Zhang, Benjamin Chang, Hao Le, Ramsin Khoshabeh, Truong Nguyen:
Human-Inspired Camera: A Novel Camera System for Computer Vision. 29-30 - Reza E. Rad, Soon Ho Choi, SungJin Kim, Behnam Samadpoor Rikan, Kang-Yoon Lee:
A 2-GHz Reconfigurable Transmitter Using A Class-D PA and A Multi-Tapped Transformer. 31-32 - Ho Won Kim, Kang-Yoon Lee:
Design of Multiplying Delay Locked Loop that prevents Harmonic Lock and is insensitive to PVT Variation. 33-34 - David Kim, Kang-Yoon Lee:
A Design of High Power SP7T and SP8T RF Switches using SOI CMOS Technology. 35-36 - Ji Hoon Song, Kang-Yoon Lee:
Design of 66.5dB IRR Baseband Analog with Filter Tuning. 37-38 - Kiho Lee, Dong-Ho Lee, Jusung Kim, Songcheol Hong:
Wideband LC VCO with 39.3 % Frequency Tuning Range for Dielectric Spectroscopy System. 39-40 - Jun Feng, Mohammadreza Beikmirza, Mohammadreza Mehrpoo, Leo C. N. de Vreede, Morteza S. Alavi:
A Versatile and Efficient 0.1-to-11 Gb/s CML Transmitter in 40-nm CMOS. 41-42 - Sanghyeon Park, Jae-Nam Kim, Seung-Ah Park, Jung-Hoon Chun:
A 30-Gb/s PAM-8 Transmitter with a 2-Tap Feed-Forward Equalizer and Background Clock Calibration. 43-44 - Hyung-Wook Lee, Kyeong-Min Ko, Jin-Ku Kang:
An 8 - 26 Gb/s Single Loop Reference-less CDR with Unrestricted Frequency Acquisition. 45-46 - Seungha Roh, Moon-Chul Choi, Deog-Kyoon Jeong:
A Maximum Eye Tracking Clock-and-Data Recovery Scheme with Golden Section Search(GSS) Algorithm in 28-nm CMOS. 47-48 - Minkyo Shim, Woonghee Lee, Yunhee Lee, Deog-Kyoon Jeong:
A Stochastic Variable Gain Amplifier Adaptation for PAM-4 signaling. 49-50 - Takumi Mizuno, Qidi Zhang, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Impacts of HLS Optimizations on Side-Channel Leakage for AES Circuits. 53-54 - Masaki Sano, Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Tongxin Yang, Tomoaki Ukezono:
Design of a 32-bit Accuracy-Controllable Approximate Multiplier for FPGAs. 55-56 - Koyu Ohata, Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Scheduling with Variable-Cycle Approximate Functional Units in High-Level Synthesis. 57-58 - Jaekyung Im, Seokhyeong Kang:
Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification. 59-60 - Yong-Zheng Wang, Ching-Yuan Yang:
A Self Synchronized-Switch Rectifier for Piezoelectric-Vibration Energy-Harvesting Systems. 61-62 - Ming-Jie Chung, Chih-Lun Lo, Po-Hung Chen:
A Single-Inductor Triple-Source Energy Harvesting Interface for Batterty-Assisted IoT Applications. 63-64 - Arcel G. Leynes, John Richard E. Hizon, Maria Theresa G. de Leon, Marc D. Rosales:
Asymmetric Charge Transfer Scheme Model in ML-SSHC with Consistent Power Extraction Improvement for Piezoelectric Energy Harvesters. 65-66 - Myeongjin Kwak, Hyoju Seo, Yongtae Kim:
Precision Exploration of Floating-Point Arithmetic for Spiking Neural Networks. 71-72 - Hwan-Jin Joo, Kee-Won Kwon:
Binary/Ternary Vector Matrix Multiplier with 3T-2R CBRAM Cell. 73-74 - Jiyoung Min, Sunmean Kim, Seokhyeong Kang:
Memcapacitor based Minimum and Maximum Gate Design. 75-76 - Dongsu Kim, Jongsun Park:
Low Energy and Error Resilient SOT-MRAM based FPGA LUT Cell. 77-78 - Wooyoung Choi, Seung-Myeong Yu, Yunha Kang, Junyoung Song:
Digital LDO with reference-less adaptive CLK generation and bit-shifting Coarse-Fine-control. 79-80 - Soonbum Song, Youngmin Kim:
Novel In-memory Computing Circuit using Muller C-element. 81-82 - Chih-Chyau Yang, Tian-Sheuan Chang:
Pre-RTL DNN Hardware Evaluator With Fused Layer Support. 83-84 - Jeong Jun Lee, Seung Il Lee, Hyun Kim:
Continual Learning for Instance Segmentation to Mitigate Catastrophic Forgetting. 85-86 - Jinyeon Kim, Jonghee Park, Sang-Seol Lee, Sung-Joon Jang:
Object Detection Network Robust to Local Illumination Variations. 87-88 - Joonhyung Kim, Jongsun Park:
A Charge-domain 10T SRAM based In-Memory-Computing Macro for Low Energy and Highly Accurate DNN inference. 89-90 - Kee Hoon Yang, Tae Seob Oh, Jae Bin Kim, JongWan Jo, Kang-Yoon Lee:
RF-DC Converter Using Loss Compensation and Adaptive Matching Network. 93-94 - Zubair Mehmood, Munkyo Seo:
A High Speed OOK Modulator at 300 GHz using LO Cancellation Technique. 95-96 - Zubair Mehmood, Waseem Abbas, Munkyo Seo:
Design of 100 GHz OOK Transceiver in 28nm CMOS Process for High Speed Communication. 99-100 - Donghyun Han, Youngkwang Lee, Sooryeong Lee, Sungho Kang:
Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC. 101-102 - Minseo Kim, Jongsun Park:
Short Word-Line Pulse with Fast Bit-Line Boosting For High Throughput 6T SRAM-based Compute In-memory Design. 103-104 - Hyunchul Park, Jongsun Park:
Local Bit-line Charge-sharing based Pre-charging SRAM for Near Threshold Voltage Operation. 105-106 - Yixuan He, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim:
A Time-Domain Computing-In-Memory Micro using Ring Oscillator. 107-108 - Seunggyu Lee, Jongho Yoon, Jakang Lee, Seokhyeong Kang:
Giga-sample Data Acquisition Method for High-speed DDR5 SDRAM. 109-110 - Menghao Guo, Tong Cheng, Li Li, Yuxiang Fu:
Optimized Method for Thermal Tracking in 3D NoC Systems by Using ANN. 111-112 - Ko-Chi Kuo:
A Fast Locking All Digital Delay Locked Loop with wide operating frequency ranged from 0.5 GHz to 1.8 GHz in 40nm Process. 113-114 - K. J. N. S. Bhargav, Sairam Palisetti, Madhav Rao:
A newton raphson method based approximate divider design for color quantization application. 115-116 - Aeri Kim, Seokhyeong Kang:
Data Protection Method for Flash Memory in Serial Peripheral Interface. 117-118 - Youngwook Lee, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Stochastic Edge Detection for Fine-Grained Progressive Precision. 119-120 - Hoyong Jung, Neungin Jeon, Young-Chan Jang:
Second-order Noise Shaping SAR ADC using 3-input Comparator with Voltage Gain Calibration. 123-124 - Behnam Samadpoor Rikan, Arash Hejazi, DaeYoung Choi, Reza E. Rad, YoungGun Pu, Kang-Yoon Lee:
12-Bit 5 MS/s SAR ADC with Split Type DAC for BLE. 125-126 - Hong-Seok Choi, Seungha Roh, Sanghee Lee, Jung-Hoon Park, Kwanghoon Lee, Young-Ha Hwang, Deog-Kyoon Jeong:
A 6b 48-GS/s Asynchronous 2b/cycle Time-Interleaved ADC in 28-nm CMOS. 127-128 - Jingchao Lan, Yan Zheng, Yimin Wu, Min Chen, Fan Ye, Junyan Ren:
A High Linearity Bootstrapped Switch with Leakage Current Suppressed for GS/s Sampling Rate ADC. 129-130 - Steven Lorenzo Mindoro, John Owen Cabuyadao, Arcel G. Leynes, Maria Sophia Ralota, Zyrel Renzo Sanchez, John Richard E. Hizon, Marc D. Rosales, Maria Theresa G. de Leon:
A CMOS Power Management Unit with Undervoltage Lockout Circuit as Startup for Piezoelectric Energy Harvesting Applications. 131-132 - Tzung-Je Lee, Yu-Wei Liu:
12 V PZE Harvesting Circuit For AUV Using Boost Converter with Resistor Matching Controller. 133-134 - Sunita M. S, Tejas Somashekhar, Shashidhar Tantry:
Adaptive ON - Time Boost Converter in 45nm for Solar Cell Applications. 135-136 - Israa Y. AbuShawish, Soliman A. Mahmoud:
Two Stage CMOS Bio-medical Amplifier Based on a highly Linear TΩ Pseudo-Resistor. 143-144 - Yukinaga Shimoda, Kota Hayashi, Daisuke Ito, Makoto Nakamura:
Feed-Forward Control of PAM4 CTLE for Optical Receivers Based on a Step Response Analysis. 145-146 - Israa Y. AbuShawish, Soliman A. Mahmoud:
Digitally Programmable Gain and Tunable Band-Width DPOTA based Bio-medical Amplifier. 147-148 - Jieun Park, Kang-Yoon Lee:
Low Noise Analog Front End for IoT Sensor. 149-150 - Minjeong Choi, Youngchang Choi, Sunmean Kim, Seokhyeong Kang:
Ternary Sense Amplifier Design for Ternary SRAM. 151-152 - Hyoju Seo, Jungwon Lee, Hyelin Seok, Yongtae Kim:
Design of an Accuracy Enhanced Imprecise Adder with Half Adder-based Approximation. 153-154 - Yunha Kang, Junyoung Song:
A 20-Gb/s Digitally Adaptive Linear Equalizer with 25dB loss for Single-ended Interfaces in 65nm CMOS. 155-156 - Lawrence Roman A. Quizon, Anastacia B. Alvarez, Christoper G. Santos, Marc D. Rosales, John Richard E. Hizon, Maria Patricia Rouelli G. Sabino:
A Voltage-Controlled Magnetic Anisotropy based True Random Number Generator. 159-160 - Shoki Kawaminami, Shigeru Yamashita:
Triple-Rail Stochastic Number and Its Applications. 161-162 - Jaejoon Yoon, Sehyeon Chung, Taewhan Kim:
Analyses of Power Staple Inserting Methodologies for Mitigating IR-Drops. 169-170 - Fern Nee Tan, Mohamad Shahrir Tamrin, Jia Yun Chuah:
Power Integrity Specification Definition for an Integrated Clock Circuit Design. 171-172 - Wenqi Zhu, Yutaro Komiyama, Kien Nguyan, Hiroo Sekiya:
PSO-based Design Procedure for Class-DE Inverter. 173-174 - Yutaro Komiyama, Shuya Matsuhashi, Wenqi Zhu, Kien Nguyen, Hiroo Sekiya:
Load-Independent Inverse Class-E Oscillator with Armstrong-Oscillator Based Topology. 175-176 - Satoshi Aoki, Takuji Kousaka, Shota Uchino, Daiki Hozumi, Hiroyuki Asahara:
An Estimation Method for Controlling Unstable Periodic Orbit Without Using Poincaré Map. 177-178 - Tsukasa Saito, Kenya Jin'no:
Ability to generate output series for Hysteresis Reservoir Computing. 179-180 - Tsuyoshi Isozaki, Yoko Uwate, Yoshifumi Nishio:
Information Transmission Focusing on Complex Networks Consisting of Oscillators. 181-182 - Naoto Yonemoto, Yoko Uwate, Yoshifumi Nishio:
Suppression of Chaos Propagation in Ladder Chaotic Circuits by Local Switching of Coupling Strength. 183-184 - Dou Hong, Jieming Ma, Ka Lok Man, Huiqing Wen, Prudence W. H. Wong:
Real-Time Characteristics Identification for Partial Shaded Photovoltaic Strings. 185-186 - Zong Jie Shen, Chun Zhao, Yina Liu, Li Yang, Cezhou Zhao:
Artificial synaptic behavior and its improvement of RRAM device with stacked solution-processed MXene layers. 187-188 - Gianfranco Avitabile, Ka Lok Man, Antonello Florio:
Power Consumption Analysis of a Fractional Approach to BANs Time Synchronization. 189-190 - Sanghyuk Lee, Youpeng Yang, Mohamed AbdelAzim Ibrahim, Changhyun Jun, Eng Gee Lim, Yujia Zhai:
Design on Smart Grid and Irrigation Management: based on Information Sharing. 191-192 - Antonello Florio, Gianfranco Avitabile:
A Linear Array Mutual Coupling Compensation Technique for Angle of Arrival Estimation. 193-194 - Tianzhu Xiong, Yongliang Zhou, Yuyao Kong, Bo Wang, An Guo, Yufei Wang, Chen Xue, Haiming Hsu, Xin Si, Jun Yang:
Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices. 195-196 - Jinshan Yue, Wenyu Sun, Huazhong Yang, Yongpan Liu:
Challenges and Opportunities of Energy-Efficient CIM SoC Design for Edge AI Devices. 197-198 - Bi Wang, Zhaohao Wang, Min Wang, Weisheng Zhao, Liang Wang, Yuanfu Zhao:
Soft Error Sensitivity of Magnetic Random Access Memory and Its Radiation Hardening Design. 199-200 - Kun Huang, Jingyuan Li, Ye Liu, Liang Chang, Jun Zhou:
A Survey on Feature Point Extraction Techniques. 201-202 - Seyoung Kim, Heechun Park, Jaeha Kim:
Safety Verification of AMS Circuits with Piecewise-Linear System Reachability Analysis. 203-206 - Jiwoo Hong, Sunghoon Kim, Jaeha Kim, Dongsuk Jeon:
Fast Automatic Circuit Optimization Using Deep Learning. 207-210 - Hanbyeol Kwon, Kwangrae Kim, Dongsuk Jeon, Ki-Seok Chung:
Reducing Refresh Overhead with In-DRAM Error Correction Codes. 211-214 - Heechun Park, Kyungjoon Chang, Jooyeon Jeong, Jaehoon Ahn, Ki-Seok Chung, Taewhan Kim:
Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology. 215-218 - Yoko Uwate, Yoshifumi Nishio, Marie Engelene J. Obien, Urs Frey:
Local and Global Activities of Izhikevich Neuron Model in Networks. 219-220 - Minh Le, Son Ngoc Truong:
Memristor Crossbar Circuits for Neuromorphic pattern Recognition. 221-222 - Liang Chang, Chenglong Li, Xin Zhao, Zixuan Zhu, Yi Tong, Shuisheng Lin, Jun Zhou:
Trend of Emerging Non-Volatile Memory for AI Processor. 223-224 - Jerald Yoo:
Body-coupled wireless power transfer and energy harvesting for wearables. 225 - Kyuho Lee:
Trends of Modern Processors for AI Acceleration. 227 - Sang-Soo Park, Dong-Hee Kim, Jun-Gu Kang, Ki-Seok Chung:
EdgeRL: A Light-Weight C/C++ Framework for On-Device Reinforcement Learning. 235-236 - Hyun Kim:
Implementation of Optimal CNN Accelerators for Mobile Devices: Algorithm, Architecture, and Memory System Co-Design. 237-238 - Eunchong Lee, Minyong Sung, Sung-Joon Jang, Jonghee Park, Sang-Seol Lee:
Memory-Centric Architecture of Neural Processing Unit for Edge Device. 240-241 - Malik Summair Asghar, Muhammad Junaid, HyungWon Kim, Saad Arslan, Syed Asmat Ali Shah:
A Digitally Controlled Analog kernel for Convolutional Neural Networks. 242-243 - Xinpeng Xing, Xueqian Shang, Senji Liu, Xinfa Zheng, Georges G. E. Gielen:
Power-efficient VCO-based ADCs for Wireless Communication Systems. 244-245 - Danfeng Zhai, Chixiao Chen, Liang Qi, Fan Ye, Junyan Ren:
Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration. 246-247 - Mingqiang Guo, Sai-Weng Sin, Rui Paulo Martins:
Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs. 248-249 - Ankesh Jain:
High speed Continuous-time Delta Sigma Modulators for Wide-band Applications: A review paper. 250-251 - Liang Qi, Tianming Ni, Xinyu Qin, Mingyi Chen, Yongfu Li, Guoxing Wang:
Continuous-time Delta-Sigma Modulators: Single-loop versus MASH. 252-253 - Kun-Chih Jimmy Chen, Cheng-Ting Chen:
High-accuracy and Low-latency Hybrid Stochastic Computing for Artificial Neural Network. 254-255 - Yimin Huang, Kai Chen, Zhuang Shao, Yichuan Bai, Yafeng Huang, Yuan Du, Li Du, Zhongfeng Wang:
LSMQ: A Layer-Wise Sensitivity-Based Mixed-Precision Quantization Method for Bit-Flexible CNN Accelerator. 256-257 - Yang Xiao, Wuyu Fan, Yuan Du, Li Du, Mau-Chung Frank Chang:
CTT-based Non-Volatile Deep Neural Network Accelerator Design. 258-259 - Po-Tsang Huang, Ting-Wei Liu, Wei Lu, Yu-Hsien Lin, Wei Hwang:
An Energy-Efficient Ring-Based CIM Accelerator using High-Linearity eNVM for Deep Neural Networks. 260-261 - Hung-Ming Chen, Cheng-En Ni, Kang-Yu Chang, Tzu-Chieh Chiang, Shih-Han Chang, Cheng-Yu Chiang, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou:
On Reconfiguring Memory-Centric AI Edge Devices for CIM. 262-263 - Xiangyu Zhang, Wenyan Su, Juan Li, Jingwei Li, Xin Lou:
Spatial Non-Maximum Suppression for Object Detection using Correlation and Dynamic Thresholds. 264-265 - Jincheng Lu, Zixuan Ou, Ziyu Liu, Cheng Han, Wenbin Ye:
Radar Based Real-Time Fall Detection System with Low Power Consumption. 266-267 - Zhiwen Zhang, Qian Gong, Yuan Cao, Cheng Yin, Enyi Yao, Yanhua Liu, Yongqing Pan:
Detecting LED Chip Surface Defects with Modified Faster R-CNN. 268-269 - Chenjie Kong, Tianming Chen, Jun Zhang, Guizhong Jiang, Yuan Shen, Pan He:
Application on Demodulation of FBG Sensing Signals using Phase Detection Algorithm of Intake and Exhaust. 270-271 - Shuang Song, Yizhao Zhou, Mengyu Li, Menglian Zhao:
A Review on Recent Development of Input Impedance Boosting for Bio-Potential Amplifiers. 272-273 - Yukai Shen, Shiwei Wang, Carolina Mora Lopez:
RRAM-Based STDP Network for Edge Computing in Wearable/Implantable Devices. 274-275 - Qiuyang Lin, Nick Van Helleptte:
PPG Sensors for The New Normal: A Review. 276-277 - Ming Gu, Fang Yuan, Jun Yan, Mingyi Chen:
High-speed EEG-Based Brain-Computer Interface with Wide Dynamic-range ADC. 278-279 - Mingyi Chen, Yuzhi Hao, Liang Qi, Yongfu Li, Jun Yan:
Implement Tunable Sub-TΩ On-chip Resistor for Vital Signal Acquisition: A Review. 280-281 - Wei-Hung Lin, Hsu-Yu Kao, Shih-Hsu Huang:
Hybrid Dynamic Fixed Point Quantization Methodology for AI Accelerators. 282-283 - Md Farhadur Reza:
Reinforcement Learning for Runtime Optimization for High Performance and Energy Efficient NoC. 284-285 - Tong Cheng, Haoyu Du, Li Li, Yuxiang Fu:
LSTM-based Temperature Prediction and Hotspot Tracking for Thermal-aware 3D NoC System. 286-287 - Tingting Zhang, Qichao Tao, Jie Han:
Solving Traveling Salesman Problems Using Ising Models with Simulated Bifurcation. 288-289 - Yu-Guang Chen, Hung-Yi Chiang, Chi-Wei Hsu, Tsung-Han Hsieh, Jing-Yang Jou:
A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions. 290-291 - Dongjun Lee, Jaeduk Han:
Design Techniques for Area-efficient Two-Stacked Current Sources in Nanometer CMOS Technology. 292-293 - Inho Jeon, Kyounghyun Min, Jinwoo Park, Jeongjin Roh, Deok-Ju Moon, Hyoung-Rae Kim:
A Constant On-Time Buck Converter with Fully Integrated Average Current Sensing Scheme. 294-295 - Muhammad Fakhri Mauludin, Dong-Ho Lee, Jusung Kim:
Wideband Operational Trans-Conductance Amplifier with Feed-Forward Compensation Technique. 298-299 - Changmin Song, Se-Hyeon Cho, Young-Chan Jang:
A 0.2 ‒ 1.2GHz Adaptive Bandwidth PLL with Controllable KVCO. 300-301 - Reza E. Rad, Behnam Samadpoor Rikan, Kang-Yoon Lee:
A 5.8 GHz RF-DC Based Energy-Harvesting Front-End with a Load-Lighting LC-Oscillator Based Voltage Booster for a SWIPT IC. 307-308 - Junghoon Jin, Seungjun Kim, Sunguk Choi, Pil-Ho Lee, Sang-jae Rhee, Ki-hwan Choi, Jongsun Kim:
A 7.68 GHz Fast-Lock Low-Jitter Digital MDLL. 311-312 - Hanh Dangba, Ngoc Thang Bui, Hae-Jin Kim, Jun-hee Song, Chaiyoon Chung, Gyung-Su Byun:
A High-speed Wireless Data Transfer for Non - Destructive Testing. 315-316 - Dong Han Ko, Sehee Lim, Young Kyu Lee, Seong-Ook Jung:
High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit. 321-322 - Donghoon Choi, Hyouk-Kyu Cha:
A Low-Power Low-Noise Neural Signal Acquisition Amplifier with Tolerance to Large Stimulation Artifacts. 325-326 - Shiyi Jin, Yeonjin Kim, Jin-Gyun Chung, Yongen Kim:
CAN Data Compression Based on Sorting and Mapping Method. 327-328 - Woo-Young Choi:
Digital Controller Implementation of Grid-Tied Zeta Inverter Using 16-bits Microcontroller. 329-330 - Chang han Rho, Jin-Ku Kang, Jin Liu:
Two-step Time-to-Digital Converter using pulse-shifting time-difference repetition circuit. 333-334 - Tae-ho Shin, Jaeduk Han:
A SCAN Chain Generator for Verification of Full-Custom Integrated Circuits. 335-336 - Geuntae Park, Youngmin Kim:
Low Power Gate Diffusion Input Full Adder using Floating Body. 337-338 - Sanghoon Lee, Daejin Park:
Efficient Power Control Using Variable Resolution Algorithm for LiDAR Sensor-based Autonomous Vehicle. 341-342 - Dongchan Lee, Youngmin Kim:
A simplified, high-speed, Error-tolerant Adder using Zero Padding Method. 343-344 - Phap Duong-Ngoc, Tuy Nguyen Tan, Hanho Lee:
Configurable Butterfly Unit Architecture for NTT/INTT in Homomorphic Encryption. 345-346 - Hyunju Kim, Hyungtak Kim, Youngmin Kim:
Low Power High Performance Match Line Design of Content Addressable Memory. 347-348 - Dongkyu Lee, Seungmin Lee, Daejin Park:
Efficient Signal Processing Acceleration using OpenCL-based FPGA-GPU Hybrid Cooperation for Reconfigurable ECG Diagnosis. 349-350 - Cheolhyeong Park, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
FPGA-based Scalable Road Image Stochastic Denosing Approach. 351-352 - Yonggang Zhang, Hui Chen, Yuxiang Fu, Li Li:
2β-softmax: A Hardware-Friendly Activation Function with Low Complexity and High Performance. 353-354 - B. S. Ajay, Madhav Rao:
Design of emotion recognition system using neuromorphic computing technique. 355-356 - Kyuhong Shim, Iksoo Choi, Wonyong Sung, Jungwook Choi:
Layer-wise Pruning of Transformer Attention Heads for Efficient Language Modeling. 357-358 - Ki Beom Lee, Sumin Lee, Sunghwan Joo, Hong Keun Ahn, Young Seok Jung, Seong-Ook Jung:
CNN encryption using XOR Gate for Hardware Optimization. 359-360 - Young Kyu Lee, Minjune Yeo, Seokhee Cho, Seong-Ook Jung:
Intrinsic Capacitance based Multi bit Computing in Memory. 361-362 - Chanhee Lee, Sangho Yoon, Seokhyeong Kang:
Components Analysis on Audio Signal Mixtures. 363-364 - Sangjun Lee, Jongho Park, Inhwan Lee, Kwonhyoung Lee, Sungho Kang:
Hybrid Test Access Mechanism for Multiple Identical Cores. 365-366 - Yilin Zhao, Qidi Zhang, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Power Side-Channel Analysis for Different Adders on FPGA. 367-368 - Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
High-Level Synthesis of Approximate Computing Circuits with Dual Accuracy Modes. 369-370 - Jaehyuk So, Dong-Hyun Lee, Min-Joon Kim, Yeon-Kug Moon:
ASIC Implementation of Magnetic Induction based Wireless Communication System. 371-372 - Soyeon Choi, Nari Im, Hoyoung Yoo:
FPGA Design Duplication based on the Bitstream Extraction. 373-374 - Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Khai-Duy Nguyen, Trong-Thuc Hoang, Koichiro Ishibashi, Cong-Kha Pham:
A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications. 375-376 - Gaeryun Sung, Jaeduk Han:
High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology. 377-378 - Yunhee Lee, Woonghee Lee, Minkyo Shim, Deog-Kyoon Jeong:
A Sequential Two-step Algorithm For DC Offset Cancellation of PAM-4 Receiver. 379-380 - Daeho Yun, Deog-Kyoon Jeong:
Auto-tracking Method with Optimal Reference Voltage for PAM-4 Receiver. 381-382 - Keun-Yong Chung, Kwang-Hyun Baek, Bo-Kyong Choi:
A SAR ADC with Segment Binary Weighted Attenuation Capacitor DAC layout technique. 389-390 - Wooyoung Lee, Jina Park, Changjun Byun, Eunjin Choi, Jae-Hyoung Lee, Woojoo Lee, Kyung Jin Byun, Kyuseung Han:
K-means Clustering-specific Lightweight RISC-V processor. 391-392 - Sunwoo Yoo, Seungwoo Hong, Youngjoo Lee:
Low-Complexity On-Device ECG Classifier using Binarized Neural Network. 393-394 - Eun-Bin Park, Taigon Song:
An Optimized Standard Cell Design Methodology Targeting Low Parasitics and Small Area for Complementary FETs (CFETs). 395-396 - SangHyun Lee, Byungin Moon:
A Haar Classifier Accelerator with Reduced Multiplexer Usage. 399-400 - Cheol-Ho Choi, Younghyeon Kim, Jiseok Ha, Byungin Moon:
Haar Filter Hardware Architecture for the Accuracy Improvement of Stereo Vision Systems. 401-402 - Tuy Nguyen Tan, Phap Duong-Ngoc, Thang Xuan Pham, Hanho Lee:
Novel Performance Evaluation Approach of AMBA AXI-Based SoC Design. 403-404 - Kyeong-Min Ko, Dohyeon Kwon, Jin-Ku Kang:
Design of 20Gb/s PAM4 Transmitter with Maximum Transition Elimination and Transition Compensation Techniques. 405-406 - Waseem Abbas, Munkyo Seo:
A Gain Boosted Single-Ended 300 GHz InP HBT Oscillator for Terahertz Applications. 407-408 - Jin-Young Hwang, Kee-Won Kwon:
A Non-linear Input Converter Inversely Pre-distorted Against Nonlinear Behavior of FG-based Neuromorphic Synaptic Devices. 409-410 - Hyun-Wook Son, YongSeok Na, TaeHyun Kim, Ali A. Al-Hamid, HyungWon Kim:
CNN Accelerator with Minimal On-Chip Memory Based on Hierarchical Array. 411-412 - Jinwon Joo, Minyong Yoon, Jungwook Choi, Mingu Kang, Jong-Geon Lee, Jinin So, IlKwon Yun, Yongsuk Kwon, KyungSoo Kim:
Understanding and Reducing Weight-Load Overhead of Systolic Deep Learning Accelerators. 413-414 - Dahun Choi, Hyun Kim:
Hardware-friendly Log-scale Quantization for CNNs with Activation Functions Containing Negative Values. 415-416 - Joon Hyeon Park, Min Cheol Kim, Byeong Dae Lee, Myung Hoon Sunwoo:
Implementation of CNN based Demosaicking on FPGA. 417-418 - Akshay Kumar Sharma, Byungho Kang, Kyung Ki Kim:
LightNet: A Lightweight Neural Network for Image Classification. 419-420 - Changseon Chae, Subin Kim, Jonghang Choi, Jun-Eun Park:
A Multi-Bit In-Memory-Computing SRAM Macro Using Column-Wise Charge Redistribution for DNN Inference in Edge Computing Devices. 421-422 - Min-Wu Jeong, Chae-Eun Rhee:
Fusion for Tile-based Deconvolution Layers. 423-424 - Seokjun Jang, Hyungil Woo, Sunghoon Kim, Sungho Kang:
Secure Scan Design through Pseudo Fault Injection. 425-426 - Younwoo Yoo, Hayoung Lee, Seung Ho Shin, Sungho Kang:
Post-bond Repair of Line Faults with Double-bit ECC for 3D Memory. 427-428 - Seung Ho Shin, Hayoung Lee, Younwoo Yoo, Sungho Kang:
An Effective Spare Allocation Methodology for 3D Memory Repair with BIRA. 429-430 - Youngki Moon, Hyunho Yoo, Donghyun Han, Sungho Kang:
Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure. 431-432
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