"Gate elimination: Circuit size lower bounds and #SAT upper bounds."

Alexander Golovnev et al. (2018)

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DOI: 10.1016/J.TCS.2017.11.008

access: closed

type: Journal Article

metadata version: 2019-09-25

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  - https://dblp.org/rec/journals/tcs/GolovnevKST18
Alexander Golovnev, Alexander S. Kulikov, Alexander V. Smal, Suguru Tamaki:
Gate elimination: Circuit size lower bounds and #SAT upper bounds. Theor. Comput. Sci. 719: 46-63 (2018)

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