"Area efficient, high speed VLSI design for BPC coder in JPEG 2000."

Refka Ghodhbani et al. (2014)

> Home

Details and statistics

DOI: 10.1109/IPAS.2014.7043276

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-07

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/ipas2/GhodhbaniSHA14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ipas2/GhodhbaniSHA14
Refka Ghodhbani, Taoufik Saidani, Layla Horrigue, Mohamed Atri:
Area efficient, high speed VLSI design for BPC coder in JPEG 2000. IPAS 2014: 1-5

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.