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2020 – today
- 2022
[c64]Christopher K. Chen
, Margo I. Seltzer, Mark R. Greenstreet:
Shellac: A Compiler Synthesizer for Concurrent Programs. VSTTE 2022: 33-51- 2020
- [c63]Justin Reiher, Mark R. Greenstreet:
Optimization and Comparison of Synchronizers. ASYNC 2020: 28-35
2010 – 2019
- 2019
- [c62]Yan Peng, Mark R. Greenstreet:
Verifying Timed, Asynchronous Circuits using ACL2. ASYNC 2019: 96-104 - [c61]Itrat A. Akhter, Justin Reiher, Mark R. Greenstreet:
Finding All DC Operating Points Using Interval Arithmetic Based Verification Algorithms. DATE 2019: 1595-1598 - [c60]Mark R. Greenstreet:
Integrating SMT with Theorem Proving for Verification of Analog and Mixed-Signal Circuits (Invited Tutorial). FMCAD 2019: 1 - 2018
- [c59]Justin Reiher, Mark R. Greenstreet, Ian W. Jones:
Explaining Metastability in Real Synchronizers. ASYNC 2018: 59-67 - [c58]Carl Kwan, Mark R. Greenstreet:
Real Vector Spaces and the Cauchy-Schwarz Inequality in ACL2(r). ACL2 2018: 111-127 - [c57]Carl Kwan, Mark R. Greenstreet:
Convex Functions in ACL2(r). ACL2 2018: 128-142 - [c56]Yan Peng, Mark R. Greenstreet:
Smtlink 2.0. ACL2 2018: 143-160 - 2017
- [c55]Ameer M. S. Abdelhadi, Mark R. Greenstreet:
Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs. ASYNC 2017: 41-48 - 2016
- [c54]Yan Peng, Ian W. Jones, Mark R. Greenstreet:
Finding Glitches Using Formal Methods. ASYNC 2016: 45-46 - 2015
- [c53]Yan Peng, Mark R. Greenstreet:
Integrating SMT with Theorem Proving for Analog/Mixed-Signal Circuit Verification. NFM 2015: 310-326 - [c52]Yan Peng, Mark R. Greenstreet:
Extending ACL2 with SMT Solvers. ACL2 2015: 61-77 - 2014
- [j14]Chao Yan, Mark R. Greenstreet, Suwen Yang:
Verifying global start-up for a Möbius ring-oscillator. Formal Methods Syst. Des. 45(2): 246-272 (2014) - [c51]Brad D. Bingham, Mark R. Greenstreet:
Response property checking via distributed state space exploration. FMCAD 2014: 15-22 - 2013
- [c50]Brad D. Bingham, Jesse D. Bingham, John Erickson, Mark R. Greenstreet:
Distributed Explicit State Model Checking of Deadlock Freedom. CAV 2013: 235-241 - [c49]Jijie Wei, Yan Peng, Ge Yu, Mark R. Greenstreet:
Verifying global convergence for a digital phase-locked loop. FMCAD 2013: 113-120 - 2012
- [j13]Brad D. Bingham, Mark R. Greenstreet:
Modeling Energy-Time Trade-Offs in VLSI Computation. IEEE Trans. Computers 61(4): 530-547 (2012) - [c48]Chao Yan, Mark R. Greenstreet:
Oscillator verification with probability one. FMCAD 2012: 165-172 - 2011
- [c47]Suwen Yang, Ian W. Jones, Mark R. Greenstreet:
Synchronizer Performance in Deep Sub-Micron Technology. ASYNC 2011: 33-42 - [c46]Brad D. Bingham, Mark R. Greenstreet, Jesse D. Bingham:
Parameterized verification of deadlock freedom in symmetric cache coherence protocols. FMCAD 2011: 186-195 - [c45]Vijay Anand Korthikanti, Gul Agha, Mark R. Greenstreet:
On the Energy Complexity of Parallel Algorithms. ICPP 2011: 562-570 - 2010
- [c44]Chao Yan, Mark R. Greenstreet, Jochen Eisinger:
Formal Verification of an Arbiter Circuit. ASYNC 2010: 165-175 - [c43]Suwen Yang, Robert J. Drost, Mark R. Greenstreet, Shahriar Mirabbasi, Frank O'Mahony:
Varactor-based signal restoration for near-speed-of-light surfing global interconnect. CICC 2010: 1-4
2000 – 2009
- 2009
- [c42]Ian W. Jones, Suwen Yang, Mark R. Greenstreet:
Synchronizer Behavior and Analysis. ASYNC 2009: 117-126 - [c41]Mark R. Greenstreet:
Verifying VLSI Circuits. ATVA 2009: 1-20 - [c40]Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet:
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. FPGA 2009: 43-52 - [c39]Tarik Ono-Tesfaye, Mark R. Greenstreet:
A modular synchronizing FIFO for NoCs. NOCS 2009: 224-233 - [c38]Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet:
Estimating reliability and throughput of source-synchronous wave-pipelined interconnect. NOCS 2009: 234-243 - 2008
- [j12]Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton:
Practical Asynchronous Interconnect Network Design. IEEE Trans. Very Large Scale Integr. Syst. 16(5): 579-588 (2008) - [c37]Chao Yan, Mark R. Greenstreet:
Faster projection based methods for circuit level verification. ASP-DAC 2008: 410-415 - [c36]Chao Yan, Mark R. Greenstreet:
Verifying an Arbiter Circuit. FMCAD 2008: 1-9 - [c35]Mark R. Greenstreet, Suwen Yang:
Verifying start-up conditions for a ring oscillator. ACM Great Lakes Symposium on VLSI 2008: 201-206 - [c34]Brad D. Bingham, Mark R. Greenstreet:
Computation with Energy-Time Trade-Offs: Models, Algorithms and Lower-Bounds. ISPA 2008: 143-152 - [c33]Brad D. Bingham, Mark R. Greenstreet:
Energy Optimal Scheduling on Multiprocessors with Migration. ISPA 2008: 153-161 - 2007
- [j11]Paul Teehan, Mark R. Greenstreet, Guy G. Lemieux:
A Survey and Taxonomy of GALS Design Styles. IEEE Des. Test Comput. 24(5): 418-428 (2007) - [j10]Suwen Yang, Brian D. Winters, Mark R. Greenstreet:
Surfing Pipelines: Theory and Implementation. IEEE J. Solid State Circuits 42(6): 1405-1414 (2007) - [j9]Jihong Ren, Chen Greif, Mark R. Greenstreet:
An efficient linear programming solver for optimal filter synthesis. Numer. Linear Algebra Appl. 14(9): 695-712 (2007) - [c32]Suwen Yang, Mark R. Greenstreet, Jihong Ren:
A Jitter Attenuating Timing Chain. ASYNC 2007: 25-38 - [c31]Suwen Yang, Mark R. Greenstreet:
Simulating Improbable Events. DAC 2007: 154-157 - [c30]Suwen Yang, Mark R. Greenstreet:
Computing synchronizer failure probabilities. DATE 2007: 1361-1366 - [c29]Chao Yan, Mark R. Greenstreet:
Circuit Level Verification of a High-Speed Toggle. FMCAD 2007: 199-206 - 2006
- [j8]Resve A. Saleh, Steven J. E. Wilton, Shahriar Mirabbasi, Alan J. Hu, Mark R. Greenstreet, Guy Lemieux, Partha Pratim Pande, Cristian Grecu, André Ivanov:
System-on-Chip: Reuse and Integration. Proc. IEEE 94(6): 1050-1069 (2006) - [c28]Mark R. Greenstreet, Jihong Ren:
Surfing Interconnect. ASYNC 2006: 98-106 - 2005
- [c27]Suwen Yang, Brian D. Winters, Mark R. Greenstreet:
Energy Efficient Surfing. ASYNC 2005: 2-11 - [c26]Jihong Ren, Mark R. Greenstreet:
A unified optimization framework for equalization filter synthesis. DAC 2005: 638-643 - [c25]Suwen Yang, Mark R. Greenstreet:
Noise margin analysis for dynamic logic circuits. ICCAD 2005: 406-412 - [c24]Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton:
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. ICCD 2005: 267-274 - [c23]Suwen Yang, Mark R. Greenstreet:
Analysing the Robustness of Surfing Circuits. FAC 2005: 65-77 - 2004
- [c22]Jihong Ren, Mark R. Greenstreet:
A Signal Integrity Test Bed for PCB Buses. ICCD 2004: 132-137 - [c21]Jihong Ren, Mark R. Greenstreet:
Crosstalk Cancellation for Realistic PCB Buses. PATMOS 2004: 48-57 - 2003
- [j7]Brian D. Winters, Mark R. Greenstreet:
Surfing: a robust form of wave pipelining using self-timed circuit techniques. Microprocess. Microsystems 27(9): 409-419 (2003) - [c20]Ajanta Chakraborty, Mark R. Greenstreet:
Efficient Self-Timed Interfaces for Crossing Clock Domains. ASYNC 2003: 78-88 - [c19]Jihong Ren, Mark R. Greenstreet:
Synthesizing optimal filters for crosstalk-cancellation for high-speed buses. DAC 2003: 592-597 - [c18]Jihong Ren, Mark R. Greenstreet:
Equalizing Filter Design for Crosstalk Cancellation. ISVLSI 2003: 272-274 - 2002
- [c17]Mark R. Greenstreet, Brian D. Winters:
A Negative-Overhead, Self-Timed Pipeline. ASYNC 2002: 37-46 - [c16]Mark R. Greenstreet, Anthony Winstanley, Aurélien Garivier:
An Event Spacing Experiment. ASYNC 2002: 47-56 - [e1]Claire J. Tomlin, Mark R. Greenstreet:
Hybrid Systems: Computation and Control, 5th International Workshop, HSCC 2002, Stanford, CA, USA, March 25-27, 2002, Proceedings. Lecture Notes in Computer Science 2289, Springer 2002, ISBN 3-540-43321-X [contents] - 2001
- [j6]Christoph Kern, Tarik Ono-Tesfaye, Mark R. Greenstreet:
A light-weight framework for hardware verification. Int. J. Softw. Tools Technol. Transf. 3(3): 286-313 (2001) - [c15]Mark R. Greenstreet, Brian de Alwis:
How to Achieve Worst-Case Performance. ASYNC 2001: 206- - [c14]Anthony Winstanley, Mark R. Greenstreet:
Temporal Properties of Self-Timed Rings. CHARME 2001: 140-154 - 2000
- [c13]Mark R. Greenstreet:
Pragmatic verification for hybrid and real-time designs. ACC 2000: 677-681
1990 – 1999
- 1999
- [j5]Christoph Kern, Mark R. Greenstreet:
Formal verification in hardware design: a survey. ACM Trans. Design Autom. Electr. Syst. 4(2): 123-193 (1999) - [c12]Mark R. Greenstreet, Tarik Ono-Tesfaye:
A Fast, asP*, RGD Arbiter. ASYNC 1999: 173-185 - [c11]Mark R. Greenstreet:
Real-Time Merging. ASYNC 1999: 186- - [c10]Mark R. Greenstreet, Ian Mitchell:
Reachability Analysis Using Polygonal Projections. HSCC 1999: 103-116 - [c9]Christoph Kern, Tarik Ono-Tesfaye, Mark R. Greenstreet:
A Light-Weight Framework for Hardware Verification. TACAS 1999: 330-344 - 1998
- [c8]Tarik Ono-Tesfaye, Christoph Kern, Mark R. Greenstreet:
Verifying a Self-Timed Divider. ASYNC 1998: 146-158 - [c7]Mark R. Greenstreet, Ian Mitchell:
Integrating Projections. HSCC 1998: 159-174 - 1997
- [c6]Peggy B. K. Pang, Mark R. Greenstreet:
Self-Timed Meshes Are Faster Than Synchronous. ASYNC 1997: 30- - 1996
- [c5]Mark R. Greenstreet:
Verifying Safety Properties of Differential Equations. CAV 1996: 277-287 - 1995
- [j4]Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger:
Automatic Verification of Asynchronous Circuits. IEEE Des. Test Comput. 12(1): 24-31 (1995) - [c4]Mark R. Greenstreet:
Implementing a STARI chip. ICCD 1995: 38-43 - 1994
- [c3]Mark R. Greenstreet, Peter Cahoon:
How fast will the flip flop? ASYNC 1994: 77-86 - [c2]Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger:
Automatic Verification of Refinement. ICCD 1994: 225-229 - 1992
- [c1]Mark R. Greenstreet:
Using Synchronized Transitions for Simulation and Timing Verification. Designing Correct Circuits 1992: 215-236 - 1990
- [j3]Mark R. Greenstreet, Kenneth Steiglitz:
Bubbles can make self-timed pipelines fast. J. VLSI Signal Process. 2(3): 139-148 (1990)
1980 – 1989
- 1988
- [j2]Jørgen Staunstrup, Mark R. Greenstreet:
From High-Level Descriptions to VLSI Circuits. BIT 28(3): 620-638 (1988) - 1987
- [j1]Mark R. Greenstreet, Peter Møller-Nielsen, Jørgen Staunstrup:
VLSI with a very low scale investment. Integr. 5(2): 125-132 (1987)
Coauthor Index
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