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Moritoshi Yasunaga
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2020 – today
- 2024
- [j24]Yusuke Yamagiwa, Yuki Kawahara, Kenji Kanazawa, Moritoshi Yasunaga:
A highly scalable Self-organizing Map accelerator on FPGA and its performance evaluation. Artif. Life Robotics 29(1): 94-100 (2024) - [c48]Jiheng Wang, Kenji Kanazawa, Moritoshi Yasunaga:
FPGA Implementation of Minimum Spanning Tree Calculation Towards Application for Capacitated Vehicle Routing Problems. ICCE 2024: 1-3 - [c47]Yusuke Yamagiwa, Kenji Kanazawa, Moritoshi Yasunaga:
A FPGA-based Learning Accelerator for Self-Organizing Map and Its Application to Trend-Visualization. ICCE 2024: 1-5
2010 – 2019
- 2019
- [c46]Kenichi Harada, Kenji Kanazawa, Moritoshi Yasunaga:
FPGA-Based Object Detection for Autonomous Driving System. FPT 2019: 465-468 - 2018
- [j23]Tetsuya Odaira, Naoki Yokoshima, Ikuo Yoshihara, Moritoshi Yasunaga:
Evolutionary design of high signal integrity interconnection based on eye-diagram. Artif. Life Robotics 23(3): 298-303 (2018) - 2016
- [j22]Moritoshi Yasunaga, Ikuo Yoshihara:
An evolutionary design methodology of printed circuit boards for high-speed VLSIs. Artif. Life Robotics 21(2): 171-176 (2016) - [j21]Shohei Sassa, Kenji Kanazawa, Shaowei Cai
, Moritoshi Yasunaga:
An FPGA Solver for Partial MaxSAT Problems Based on Stochastic Local Search. SIGARCH Comput. Archit. News 44(4): 32-37 (2016) - [c45]Moritoshi Yasunaga, Naoki Yokoshima, Ikuo Yoshihara:
A passive equalizer and its design methodology for global interconnects in VLSIs. VLSI-SoC 2016: 1-6 - 2015
- [j20]Moritoshi Yasunaga:
Foreword. IEICE Trans. Inf. Syst. 98-D(9): 1621 (2015) - [c44]Kenji Kanazawa, Kahori Kemmotsu, Yamato Mori, Noriyuki Aibe, Moritoshi Yasunaga:
High-Speed Calculation of Convex Hull in 2D Images Using FPGA. PARCO 2015: 533-542 - [c43]Moritoshi Yasunaga, Yusuke Kuribara, Hirofumi Inoue, Ikuo Yoshihara:
Simultaneous Improvement to Signal Integrity and Electromagnetic Interference in High-Speed Transmission Lines. SSCI 2015: 1236-1243 - 2014
- [c42]Moritoshi Yasunaga, Hiroki Shimada, Katsuyuki Seki, Ikuo Yoshihara:
Segmental transmission line: Its practical application the optimized PCB trace design using a genetic algorithm. ICES 2014: 23-30 - 2011
- [j19]Hiroki Shimada, Shohei Akita, Masami Ishiguro, Noriyuki Aibe, Ikuo Yoshihara, Moritoshi Yasunaga:
Digital-signal-waveform improvement on VLSI packaging including inductances. Artif. Life Robotics 16(2): 194-197 (2011) - 2010
- [j18]Masami Ishiguro, Hiroshi Nakayama, Yuki Shimauchi, Noriyuki Aibe, Ikuo Yoshihara, Moritoshi Yasunaga:
Signal-integrity improvement method and its robustness evaluation for VLSI and VLSI-packaging. Artif. Life Robotics 15(3): 325-329 (2010) - [j17]Masafumi Kuroda, Kunihito Yamamori, Masaharu Munetomo, Moritoshi Yasunaga, Ikuo Yoshihara:
Development of a novel crossover of hybrid genetic algorithms for large-scale traveling salesman problems. Artif. Life Robotics 15(4): 547-550 (2010) - [c41]Masafumi Kuroda, Kunihito Yamamori, Masaharu Munetomo, Moritoshi Yasunaga, Ikuo Yoshihara:
A proposal for Zoning Crossover of Hybrid Genetic Algorithms for large-scale traveling salesman problems. IEEE Congress on Evolutionary Computation 2010: 1-6
2000 – 2009
- 2009
- [j16]Keiko Ikeda, Moritoshi Yasunaga, Yoshiki Yamaguchi, Yorihisa Yamamoto, Ikuo Yoshihara:
A visual-inspection system using a self-organizing map. Artif. Life Robotics 14(4): 506-510 (2009) - 2008
- [j15]Naoki Koizumi, Kazuya Hayashi, Moritoshi Yasunaga, Kunihito Yamamori, Ikuo Yoshihara:
Variable-length segmental transmission line and its design guidelines. Artif. Life Robotics 12(1-2): 214-218 (2008) - [j14]Moritoshi Yasunaga, Noriyuki Aibe, Yoshiki Yamaguchi, Yorihisa Yamamoto, Takaaki Awano, Ikuo Yoshihara:
A reconfigurable VLSI-based double-lens tracking camera. Artif. Life Robotics 12(1-2): 219-222 (2008) - [j13]Moritoshi Yasunaga, Noriyuki Aibe, Yoshiki Yamaguchi, Yorihisa Yamamoto, Takaaki Awano, Ikuo Yoshihara:
Real-world applications on the reconfigurable-VLSI-based double-lens tracking-camera. Artif. Life Robotics 13(1): 73-76 (2008) - [c40]Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga, Kyrre Glette, Jim Tørresen:
An adaptive pattern recognition hardware with on-chip shift register-based partial reconfiguration. FPT 2008: 169-176 - [c39]Moritoshi Yasunaga, Yoshiki Yamaguchi, Hiroshi Nakayama, Ikuo Yoshihara, Naoki Koizumi, Jung Hwan Kim:
The Segmental-Transmission-Line: Its Design and Prototype Evaluation. ICES 2008: 130-140 - 2007
- [j12]Yoshiki Yamaguchi, Moritoshi Yasunaga, Kazuya Hayashi, Noriyuki Aibe, Yorihisa Yamamoto, Ikuo Yoshihara:
A bio-inspired tracking camera system. Artif. Life Robotics 11(1): 128-134 (2007) - [j11]Hung Dinh Nguyen, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga:
A New Three-Level Tree Data Structure for Representing TSP Tours in the Lin-Kernighan Heuristic. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(10): 2187-2193 (2007) - [j10]Hung Dinh Nguyen, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga:
Implementation of an Effective Hybrid GA for Large-Scale Traveling Salesman Problems. IEEE Trans. Syst. Man Cybern. Part B 37(1): 92-99 (2007) - [j9]Yoshiki Yamaguchi, Tsutomu Maruyama, Ryuzo Azuma
, Moritoshi Yasunaga, Akihiko Konagaya:
Mesoscopic-level Simulation of Dynamics and Interactions of Biological Molecules Using Monte Carlo Simulation. J. VLSI Signal Process. 48(3): 287-299 (2007) - [c38]Kyrre Glette, Jim Tørresen, Moritoshi Yasunaga:
Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA. AHS 2007: 463-470 - [c37]Kyrre Glette, Jim Tørresen, Moritoshi Yasunaga:
An Online EHW Pattern Recognition System Applied to Face Image Recognition. EvoWorkshops 2007: 271-280 - [c36]Kyrre Glette, Jim Tørresen, Moritoshi Yasunaga:
An Online EHW Pattern Recognition System Applied to Sonar Spectrum Classification. ICES 2007: 1-12 - [c35]Yoshiki Yamaguchi, Noriyuki Aibe, Moritoshi Yasunaga, Yorihisa Yamamoto, Takaaki Awano, Ikuo Yoshihara:
Bio-Inspired Functional Asymmetry Camera System. ICONIP (2) 2007: 637-646 - [c34]Yusuke Arai, Ryo Sawai, Yoshiki Yamaguchi, Tsutomu Maruyama, Moritoshi Yasunaga:
A Lattice Gas Cellular Automata Simulator on the Cell Broadband Engine. PARCO 2007: 459-466 - 2006
- [c33]Kyrre Glette, Jim Tørresen, Moritoshi Yasunaga, Yoshiki Yamaguchi:
On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition. AHS 2006: 373-380 - [c32]Naoki Koizumi, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga:
Enhancement of the Variable-Length-Transmission-Line design method for multi-point optimization. IEEE Congress on Evolutionary Computation 2006: 142-148 - [c31]Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga:
Realization of the sound space environment for the radiation-tolerant space craft. ReConFig 2006: 198-205 - 2005
- [c30]Naoki Koizumi, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga:
Variable length segmental-transmission-line and its parameter optimization based on GA. Congress on Evolutionary Computation 2005: 1576-1582 - [c29]Daekwan Seo, Moritoshi Yasunaga, Insook Kim, Byungwoon Ham, Jung Hwan Kim:
Finding transcriptional regulatory elements in Dictyostelium gene expression. Congress on Evolutionary Computation 2005: 1746-1752 - 2004
- [j8]Hanxi Zhu, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga:
A multimodal neural network with single-state predictions for protein secondary structure. Artif. Life Robotics 8(2): 168-173 (2004) - [j7]Hanxi Zhu, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga:
A multimodal neural network with single-state predictions for protein secondary structure. Artif. Life Robotics 8(2): 168-173 (2004) - [j6]Noriyuki Aibe, Ryosuke Mizuno, Masanori Nakamura, Moritoshi Yasunaga, Ikuo Yoshihara:
Performance evaluation system for probabilistic neural network hardware. Artif. Life Robotics 8(2): 208-213 (2004) - [j5]Noriyuki Aibe, Ryosuke Mizuno, Masanori Nakamura, Moritoshi Yasunaga, Ikuo Yoshihara:
Performance evaluation system for probabilistic neural network hardware. Artif. Life Robotics 8(2): 208-213 (2004) - [j4]Hanxi Zhu, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga:
Multi-Modal Neural Networks for Symbolic Sequence Pattern Classification. IEICE Trans. Inf. Syst. 87-D(7): 1943-1952 (2004) - [c28]Daekwan Seo, Moritoshi Yasunaga, Jung Hwan Kim:
A computational approach to detect regulatory elements in Dictyostelium discoideum. IEEE Congress on Evolutionary Computation 2004: 1647-1653 - [c27]Noriyuki Aibe, Moritoshi Yasunaga:
Reconfigurable I/O interface for mobile equipments. FPT 2004: 359-362 - 2003
- [c26]Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim:
The design of segmental-transmission-line for high-speed digital signals using genetic algorithms. IEEE Congress on Evolutionary Computation 2003: 1748-1755 - [c25]Hung Dinh Nguyen, Kunihito Yamamori, Ikuo Yoshihara, Moritoshi Yasunaga:
Improved GA-based method for multiple protein sequence alignment. IEEE Congress on Evolutionary Computation 2003: 1826-1832 - [c24]Noriyuki Aibe, Moritoshi Yasunaga:
Reconfigurable parallel comparation architecture and its application to IP packet filters. FPT 2003: 363-366 - [c23]Ryosuke Mizuno, Noriyuki Aibe, Moritoshi Yasunaga, Ikuo Yoshihara:
Reconfigurable architecture for probabilistic neural network system. FPT 2003: 367-370 - [c22]Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim:
Gene Finding Using Evolvable Reasoning Hardware. ICES 2003: 198-207 - 2002
- [c21]Moritoshi Yasunaga, Kentaro Ushiyama, Noriyuki Aibe, Hidetoshi Fujiwara, Ikuo Yoshiyara, Jung H. Kim:
An evolutionary kernel-based reasoning system using reconfigurable VLSIs: its hardware prototyping and application to the splicing boundary problem. IEEE Congress on Evolutionary Computation 2002: 285-290 - [c20]Hung Dinh Nguyen, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga:
A parallel hybrid genetic algorithm for multiple protein sequence alignment. IEEE Congress on Evolutionary Computation 2002: 309-314 - [c19]Hanxi Zhu, Ikuo Yoshihara, Kunihito Yamamori, Moritoshi Yasunaga:
Prediction of protein secondary Structure by Multi-Modal Neural Networks. SEAL 2002: 682-697 - 2001
- [j3]Moritoshi Yasunaga, Jung Hwan Kim, Ikuo Yoshihara:
Evolvable Reasoning Hardware: Its Prototyping and Performance Evaluation. Genet. Program. Evolvable Mach. 2(3): 211-230 (2001) - [j2]Jung Hwan Kim, Shanuj V. Sarin, Moritoshi Yasunaga, Hyunseo Oh:
Robust noncoherent PN-code acquisition for CDMA communication systems. IEEE Trans. Veh. Technol. 50(1): 278-286 (2001) - [c18]Moritoshi Yasunaga, Takahiro Tsuzuku, Kentaro Ushiyama, Ikuo Yoshihara, Jung H. Kim:
Evolvable reasoning hardware: its application to the genome informatics. CEC 2001: 704-711 - [e1]Yong Liu, Kiyoshi Tanaka, Masaya Iwata, Tetsuya Higuchi, Moritoshi Yasunaga:
Evolvable Systems: From Biology to Hardware, 4th International Conference, ICES 2001 Tokyo, Japan, October 3-5, 2001, Proceedings. Lecture Notes in Computer Science 2210, Springer 2001, ISBN 3-540-42671-X [contents] - 2000
- [c17]Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, Jung H. Kim:
GA-based kernel optimization for pattern recognition: theory for EHW application. CEC 2000: 545-552 - [c16]Ikuo Yoshihara, Tomoo Aoyama, Moritoshi Yasunaga:
GP-based modeling method for time series prediction with parameter optimization and node alternation. CEC 2000: 1475-1481 - [c15]Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim:
A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI. DFT 2000: 69-77 - [c14]Moritoshi Yasunaga, Taro Nakamura, Jung Hwan Kim, Ikuo Yoshihara:
Kernel-Based Pattern Recognition Hardware: Its Design Methodology Using Evolved Truth Tables. Evolvable Hardware 2000: 253-262 - [c13]Moritoshi Yasunaga, Jung Hwan Kim, Ikuo Yoshihara:
The application of genetic algorithms to the design of reconfigurable reasoning VLSI chips. FPGA 2000: 116-125 - [c12]Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, Jung Hwan Kim:
Kernel Optimization in Pattern Recognition Using a Genetic Algorithm. GECCO 2000: 391 - [c11]Ikuo Yoshihara, Tomoo Aoyama, Moritoshi Yasunaga:
A Fast Model-Building Method for Time Series Using Genetic Programming. GECCO 2000: 537 - [c10]Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara, Jung Hwan Kim:
Genetic Algorithm-Based Methodology for Pattern Recognition Hardware. ICES 2000: 264-273
1990 – 1999
- 1999
- [c9]Moritoshi Yasunaga, Kenichi Tominaga, Jung Hwan Kim:
Parallel self-organization map using multiple stimuli. IJCNN 1999: 1127-1130 - [c8]Moritoshi Yasunaga, Taro Nakamura, Ikuo Yoshihara:
Sonar spectrum recognition chip designed by evolutionary algorithm. IJCNN 1999: 3182-3187 - [c7]Ikuo Yoshihara, Tomoyuki Nakagawa, Moritoshi Yasunaga, Kenichi Abe:
A multi-modal neural network using Chebyschev polynomials and its application. IJCNN 1999: 4099-4102 - [c6]Moritoshi Yasunaga, Eiji Yoshida, Ikuo Yoshihara:
Parallel back-propagation using genetic algorithm: real-time BP learning on the massively parallel computer CP-PACS. IJCNN 1999: 4175-4180 - 1998
- [j1]Moritoshi Yasunaga, I. Hachiya, K. Moki, Jung Hwan Kim:
Fault-tolerant self-organizing map implemented by wafer-scale integration. IEEE Trans. Very Large Scale Integr. Syst. 6(2): 257-265 (1998) - [c5]Hirokazu Koizumi, T. Ochiai, T. Okahashi, Y. Yamashita, A. Maki, T. Yamamoto, Y. Inagami, H. Yoshizawa, Masaya Iwata, Takashi Omori, Moritoshi Yasunaga:
Dynamic Optical Topography and the Real-Time PDP Chip: An Analytical and Synthetical Approach to Higher-Order Brain Functions. ICONIP 1998: 337-340 - [c4]Moritoshi Yasunaga, Akio Yamada, T. Okahashi:
Performance of a bus-based parallel computer with integer-representation processors applied to artificial neural network and parallel AI domains. KES (3) 1998: 519-527 - 1997
- [c3]Moritoshi Yasunaga, Yuzo Hirai:
Ising model calculation using PDM neural network hardware: Boltzmann statistical mechanics embedded in the hardware. ICNN 1997: 948-952 - 1992
- [c2]Hiroaki Kitano, Moritoshi Yasunaga:
Wafer Scale Integration for Massively Parallel Memory-Based Reasoning. AAAI 1992: 850-856 - 1990
- [c1]Moritoshi Yasunaga, Noboru Masuda, Masayoshi Yagyu, Mitsuo Asai, Minoru Yamada, Akira Masaki:
Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed on 576 digital neurons. IJCNN 1990: 527-535
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