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ORCIDCheng-Kok Koh
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- affiliation: Purdue University, West Lafayette, USA
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2020 – today
- 2022
[j44]Supriyo Maji
, Cheng-Kok Koh:
A Scalable, Memory-Efficient Algorithm for Minimum Cycle Mean Calculation in Directed Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1943-1956 (2022)- 2021
- [j43]Supriyo Maji, Cheng-Kok Koh:
A Scalable Buffer Queue Sizing Algorithm for Latency Insensitive Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(11): 2386-2399 (2021) - [i1]Akshay Jajoo, Rohan Gandhi, Y. Charlie Hu, Cheng-Kok Koh:
Saath: Speeding up CoFlows by Exploiting the Spatial Dimension. CoRR abs/2111.08572 (2021)
2010 – 2019
- 2019
- [j42]Rickard Ewetz, Cheng-Kok Koh:
Scalable Construction of Clock Trees With Useful Skew and High Timing Quality. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1161-1174 (2019) - 2018
- [c109]Chuan Yean Tan, Rickard Ewetz, Cheng-Kok Koh:
Clustering of flip-flops for useful-skew clock tree synthesis. ASP-DAC 2018: 507-512 - 2017
- [j41]Rickard Ewetz, Cheng-Kok Koh:
Fast clock scheduling and an application to clock tree synthesis. Integr. 56: 115-127 (2017) - [c108]Szu-Yuan Han, Wen-Hao Liu, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang:
Delay-driven layer assignment for advanced technology nodes. ASP-DAC 2017: 456-462 - [c107]Akshay Jajoo, Rohan Gandhi, Y. Charlie Hu, Cheng-Kok Koh:
Saath: Speeding up CoFlows by Exploiting the Spatial Dimension. CoNEXT 2017: 439-450 - [c106]Rickard Ewetz, Cheng-Kok Koh:
Clock Tree Construction based on Arrival Time Constraints. ISPD 2017: 67-74 - 2016
- [j40]Rickard Ewetz, Cheng-Kok Koh:
Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Compression. ACM Trans. Design Autom. Electr. Syst. 21(4): 57:1-57:27 (2016) - [j39]Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee:
An Automatic Design of Factors in a Human-Pose Estimation System Using Neural Networks. IEEE Trans. Syst. Man Cybern. Syst. 46(7): 875-887 (2016) - [c105]Rickard Ewetz, Cheng-Kok Koh:
MCMM clock tree optimization based on slack redistribution using a reduced slack graph. ASP-DAC 2016: 366-371 - [c104]Rickard Ewetz, Chuan Yean Tan, Cheng-Kok Koh:
Construction of Latency-Bounded Clock Trees. ISPD 2016: 81-88 - 2015
- [j38]Rickard Ewetz, Cheng-Kok Koh:
Cost-Effective Robustness in Clock Networks Using Near-Tree Structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 515-528 (2015) - [c103]Rickard Ewetz, Shankarshana Janarthanan, Cheng-Kok Koh:
Fast clock skew scheduling based on sparse-graph algorithms. ASP-DAC 2015: 472-477 - [c102]Rickard Ewetz, Shankarshana Janarthanan, Cheng-Kok Koh:
Construction of reconfigurable clock trees for MCMM designs. DAC 2015: 25:1-25:6 - [c101]Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee:
Human-pose estimation with neural-network realization. IROS 2015: 4059-4064 - [c100]Rickard Ewetz, Cheng-Kok Koh:
A Useful Skew Tree Framework for Inserting Large Safety Margins. ISPD 2015: 85-92 - [c99]Rohan Gandhi, Y. Charlie Hu, Cheng-Kok Koh, Hongqiang Harry Liu, Ming Zhang:
Rubik: Unlocking the Power of Locality and End-point Flexibility in Cloud Scale Load Balancing. USENIX ATC 2015: 473-485 - 2014
- [j37]Cheng-Kok Koh, Chin Ngai Sze:
Guest Editorial Special Section on Contemporary and Emerging Issues in Physical Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 493-494 (2014) - [j36]Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee:
A 3-D-Point-Cloud System for Human-Pose Estimation. IEEE Trans. Syst. Man Cybern. Syst. 44(11): 1486-1497 (2014) - [j35]Ao-Jan Su, Y. Charlie Hu, Aleksandar Kuzmanovic, Cheng-Kok Koh:
How to Improve Your Search Engine Ranking: Myths and Reality. ACM Trans. Web 8(2): 8:1-8:25 (2014) - [c98]Shuai Li, Cheng-Kok Koh:
Analytical placement of mixed-size circuits for better detailed-routability. ASP-DAC 2014: 41-46 - [c97]Rickard Ewetz, Anirudh Udupa, Ganesh Subbarayan, Cheng-Kok Koh:
A TSV-cross-link-based approach to 3D-clock network synthesis for improved robustness. ACM Great Lakes Symposium on VLSI 2014: 15-20 - [c96]Rickard Ewetz, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang, Cheng-Kok Koh:
A study on the use of parallel wiring techniques for sub-20nm designs. ACM Great Lakes Symposium on VLSI 2014: 129-134 - [c95]Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee:
Selecting best viewpoint for human-pose estimation. ICRA 2014: 4844-4849 - [c94]Shuai Li, Cheng-Kok Koh:
MIP-based detailed placer for mixed-size circuits. ISPD 2014: 11-18 - 2013
- [j34]Yiran Chen, Weng-Fai Wong, Hai Li, Cheng-Kok Koh, Yaojun Zhang, Wujie Wen:
On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations. ACM J. Emerg. Technol. Comput. Syst. 9(2): 16:1-16:22 (2013) - [j33]Anirudh Udupa, Ganesh Subbarayan, Cheng-Kok Koh:
Analytical estimates of stress around a doubly periodic arrangement of through-silicon vias. Microelectron. Reliab. 53(1): 63-69 (2013) - [j32]Jiang Hu, Cheng-Kok Koh:
Guest editorial: Special section on cross-domain physical optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 173-174 (2013) - [c93]Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li:
Optimization of placement solutions for routability. DAC 2013: 153:1-153:9 - [c92]Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee:
A 3D-point-cloud feature for human-pose estimation. ICRA 2013: 1623-1628 - [c91]Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee:
Using action classification for human-pose estimation. IROS 2013: 1176-1181 - [c90]Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li:
Case study for placement solutions in ispd11 and dac12 routability-driven placement contests. ISPD 2013: 114-119 - [c89]Rickard Ewetz, Cheng-Kok Koh:
Local merges for effective redundancy in clock networks. ISPD 2013: 162-167 - [c88]Kai-Chi Chan, Cheng-Kok Koh, C. S. George Lee:
Collaborative object tracking with motion similarity measure. ROBIO 2013: 964-969 - [e3]Cheng-Kok Koh, Cliff C. N. Sze:
International Symposium on Physical Design, ISPD'13, Stateline, NV, USA, March 24-27, 2013. ACM 2013, ISBN 978-1-4503-1954-6 [contents] - 2012
- [j31]Stephen Cauley, Venkataramanan Balakrishnan, Gerhard Klimeck, Cheng-Kok Koh:
A two-dimensional domain decomposition technique for the simulation of quantum-scale devices. J. Comput. Phys. 231(4): 1293-1313 (2012) - [j30]Jiang Hu, Cheng-Kok Koh:
Guest Editorial Special Section on the 2011 International Symposium on Physical Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 165-166 (2012) - [j29]Jongwon Lee, Duo Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Dan Jiao:
A Quadratic Eigenvalue Solver of Linear Complexity for 3-D Electromagnetics-Based Analysis of Large-Scale Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(3): 380-390 (2012) - [j28]Yuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, Guoyong Shi, Grantham K. H. Pang, Ngai Wong:
Passivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(4): 532-545 (2012) - [c87]Wen-Hao Liu, Yih-Lang Li, Cheng-Kok Koh:
A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing. ICCAD 2012: 713-719 - [c86]Shuai Li, Cheng-Kok Koh:
Mixed integer programming models for detailed placement. ISPD 2012: 87-94 - [c85]Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan:
A size scaling approach for mixed-size placement. ISPD 2012: 201-206 - [e2]Jiang Hu, Cheng-Kok Koh:
International Symposium on Physical Design, ISPD'12, Napa, CA, USA, March 25-28, 2012. ACM 2012, ISBN 978-1-4503-1167-0 [contents] - 2011
- [j27]Yijiang Shen, Ngai Wong, Edmund Y. Lam, Cheng-Kok Koh:
Finite difference schemes for heat conduction analysis in integrated circuit design and manufacturing. Int. J. Circuit Theory Appl. 39(9): 905-921 (2011) - [j26]Stephen Cauley, Venkataramanan Balakrishnan, Y. Charlie Hu, Cheng-Kok Koh:
A parallel branch-and-cut approach for detailed placement. ACM Trans. Design Autom. Electr. Syst. 16(2): 18:1-18:19 (2011) - [c84]Shing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao:
Simultaneous redundant via insertion and line end extension for yield optimization. ASP-DAC 2011: 633-638 - [c83]Yiran Chen, Weng-Fai Wong, Hai Li, Cheng-Kok Koh:
Processor caches with multi-level spin-transfer torque ram cells. ISLPED 2011: 73-78 - [c82]Tarun Mittal, Cheng-Kok Koh:
Cross link insertion for improving tolerance to variations in clock network synthesis. ISPD 2011: 29-36 - [c81]Shashank Bujimalla, Cheng-Kok Koh:
Synthesis of low power clock trees for handling power-supply variations. ISPD 2011: 37-44 - 2010
- [j25]Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao:
Optimal Double Via Insertion With On-Track Preference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 318-323 (2010) - [j24]Stephen Cauley, Venkataramanan Balakrishnan, Cheng-Kok Koh:
A Parallel Direct Solver for the Simulation of Large-Scale Power/Ground Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(4): 636-641 (2010) - [j23]Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy:
Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Trans. Very Large Scale Integr. Syst. 18(11): 1621-1624 (2010) - [c80]Yuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, Grantham K. H. Pang, Ngai Wong:
PEDS: Passivity enforcement for descriptor systems via Hamiltonian-symplectic matrix pencil perturbation. ICCAD 2010: 800-807 - [c79]Ao-Jan Su, Y. Charlie Hu, Aleksandar Kuzmanovic, Cheng-Kok Koh:
How to Improve Your Google Ranking: Myths and Reality. Web Intelligence 2010: 50-57
2000 – 2009
- 2009
- [j22]Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li:
Tolerating process variations in large, set-associative caches: The buddy cache. ACM Trans. Archit. Code Optim. 6(2): 8:1-8:34 (2009) - [j21]Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh:
Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies. IEEE Trans. Very Large Scale Integr. Syst. 17(12): 1749-1752 (2009) - [c78]Wenwen Chai, Dan Jiao, Cheng-Kok Koh:
A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction. DAC 2009: 752-757 - [c77]Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan:
A study of routability estimation and clustering in placement. ICCAD 2009: 363-366 - [c76]Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li:
The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies. ICCD 2009: 268-274 - 2008
- [j20]Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao:
Fast and Optimal Redundant Via Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2197-2208 (2008) - [c75]Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan:
Guiding global placement with wire density. ICCAD 2008: 212-217 - [c74]Jitesh Jain, Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan:
A fast band matching technique for impedance extraction. ISCAS 2008: 2981-2984 - [c73]Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao:
Optimal post-routing redundant via insertion. ISPD 2008: 111-117 - [r1]Cheng-Kok Koh, Evangeline F. Y. Young, Yao-Wen Chang:
Global Interconnect Planning. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [j19]Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden:
Routability-Driven Placement and White Space Allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 858-871 (2007) - [j18]Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan:
Corrections to "Exact and Numerically Stable Closed-Form Expressions for Potential Coefficients of Rectangular Conductors". IEEE Trans. Circuits Syst. II Express Briefs 54-II(11): 1024 (2007) - [j17]Ruibing Lu, Aiqun Cao, Cheng-Kok Koh:
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. IEEE Trans. Very Large Scale Integr. Syst. 15(1): 69-79 (2007) - [c72]Ruilin Wang, Cheng-Kok Koh:
A frequency-domain technique for statistical timing analysis of clock meshes. ICCAD 2007: 334-339 - [c71]Hong Li, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan:
A fast band-matching technique for interconnect inductance modeling. ICCAD 2007: 568-571 - [c70]Weng-Fai Wong, Cheng-Kok Koh, Yiran Chen, Hai Li:
VOSCH: Voltage scaled cache hierarchies. ICCD 2007: 496-503 - [c69]Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh:
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. ISLPED 2007: 195-200 - [c68]Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen:
Statistical Timing Analysis Considering Spatial Correlations. ISQED 2007: 102-107 - [c67]Hong Li, Jitesh Jain, Venkataramanan Balakrishnan, Cheng-Kok Koh:
Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky Factorization. ISQED 2007: 627-632 - [c66]Chen Li, Cheng-Kok Koh:
Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement. ISQED 2007: 829-834 - 2006
- [j16]Ruibing Lu, Cheng-Kok Koh:
Performance analysis of latency-insensitive systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 469-483 (2006) - [j15]Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh, Tung-Sang Ng:
Two Algorithms for Fast and Accurate Passivity-Preserving Model Order Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2062-2075 (2006) - [j14]Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan:
Exact and numerically stable closed-form expressions for potential coefficients of rectangular conductors. IEEE Trans. Circuits Syst. II Express Briefs 53-II(6): 458-462 (2006) - [j13]Aiqun Cao, Ruibing Lu, Chen Li, Cheng-Kok Koh:
Postlayout optimization for synthesis of Domino circuits. ACM Trans. Design Autom. Electr. Syst. 11(4): 797-821 (2006) - [c65]Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh:
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. ASP-DAC 2006: 158-163 - [c64]Jitesh Jain, Stephen Cauley, Cheng-Kok Koh, Venkataramanan Balakrishnan:
SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices. ASP-DAC 2006: 422-427 - [c63]Ya-Chi Yang, Cheng-Kok Koh, Venkataramanan Balakrishnan:
Adaptive admittance-based conductor meshing for interconnect analysis. ASP-DAC 2006: 509-514 - [c62]Ruilin Wang, Cheng-Kok Koh, Byunghoo Jung, William J. Chappell:
Clock Generation and Distribution Using Traveling-Wave Oscillators with Reflection and Regeneration. CICC 2006: 781-784 - [c61]Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh:
Stable and compact inductance modeling of 3-D interconnect structures. ICCAD 2006: 1-6 - 2005
- [j12]Ameya R. Agnihotri, Satoshi Ono, Chen Li, Mehmet Can Yildiz, Ateen Khatkhate, Cheng-Kok Koh, Patrick H. Madden:
Mixed block placement via fractional cut recursive bisection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5): 748-761 (2005) - [j11]Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy:
Synthesis of skewed logic circuits. ACM Trans. Design Autom. Electr. Syst. 10(2): 205-228 (2005) - [j10]Yiran Chen, Kaushik Roy, Cheng-Kok Koh:
Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 13(1): 75-85 (2005) - [c60]Yongxin Zhu, Weng-Fai Wong, Cheng-Kok Koh:
A Performance and Power Co-optimization Approach for Modern Processors. CIT 2005: 822-828 - [c59]Aiqun Cao, Ruibing Lu, Cheng-Kok Koh:
Post-layout logic duplication for synthesis of domino circuits with complex gates. ASP-DAC 2005: 260-265 - [c58]Chen Li, Cheng-Kok Koh, Patrick H. Madden:
Floorplan management: incremental placement for gate sizing and buffer insertion. ASP-DAC 2005: 349-354 - [c57]Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh, Guoan Zhong:
Compact and stable modeling of partial inductance and reluctance matrices. ASP-DAC 2005: 507-510 - [c56]Wai-Ching Douglas Lam, Cheng-Kok Koh:
Process variation robust clock tree routing. ASP-DAC 2005: 606-611 - [c55]Ruibing Lu, Aiqun Cao, Cheng-Kok Koh:
Improving the scalability of SAMBA bus architecture. ASP-DAC 2005: 1164-1167 - [c54]Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh:
Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologies. CICC 2005: 775-778 - [c53]Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh:
3D module placement for congestion and power noise reduction. ACM Great Lakes Symposium on VLSI 2005: 458-461 - [c52]Wai-Ching Douglas Lam, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen:
Statistical based link insertion for robust clock network design. ICCAD 2005: 588-591 - [c51]Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh:
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design. ISLPED 2005: 115-118 - 2004
- [c50]Ruibing Lu, Cheng-Kok Koh:
A high performance bus communication architecture through bus splitting. ASP-DAC 2004: 751-755 - [c49]Yiran Chen, Kaushik Roy, Cheng-Kok Koh:
Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. ASP-DAC 2004: 893-898 - [c48]Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh:
Passivity-preserving model reduction via a computationally efficient project-and-balance scheme. DAC 2004: 369-374 - [c47]Aiqun Cao, Cheng-Kok Koh:
Post-layout logic optimization of domino circuits. DAC 2004: 820-825 - [c46]Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh, Tung-Sang Ng:
A fast Newton/Smith algorithm for solving algebraic Riccati equations and its application in model order reduction. ICASSP (5) 2004: 53-56 - [c45]Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan:
Fast simulation of VLSI interconnects. ICCAD 2004: 93-98 - [c44]Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden:
Routability-driven placement and white space allocation. ICCAD 2004: 394-401 - [c43]Ateen Khatkhate, Chen Li, Ameya R. Agnihotri, Mehmet Can Yildiz, Satoshi Ono, Cheng-Kok Koh, Patrick H. Madden:
Recursive bisection based mixed block placement. ISPD 2004: 84-89 - 2003
- [j9]Guoan Zhong, Cheng-Kok Koh, Kaushik Roy:
On-chip interconnect modeling by wire duplication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1521-1532 (2003) - [c42]Guoan Zhong, Cheng-Kok Koh, Kaushik Roy:
A metric for analyzing effective on-chip inductive coupling. ASP-DAC 2003: 156-161 - [c41]Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy:
Integer linear programming-based synthesis of skewed logic circuits. ASP-DAC 2003: 820-823 - [c40]Guoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy:
An adaptive window-based susceptance extraction and its efficient implementation. DAC 2003: 728-731 - [c39]Ruibing Lu, Cheng-Kok Koh:
Interconnect Planning with Local Area Constrained Retiming. DATE 2003: 10442-10447 - [c38]Ruibing Lu, Cheng-Kok Koh:
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. ICCAD 2003: 8-12 - [c37]Ruibing Lu, Cheng-Kok Koh:
Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels. ICCAD 2003: 227-231 - [c36]Aiqun Cao, Cheng-Kok Koh:
Non-Crossing OBDDs for Mapping to Regular Circuit Structures. ICCD 2003: 338-343 - [c35]Yiran Chen, Kaushik Roy, Cheng-Kok Koh:
Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. ISLPED 2003: 229-234 - [c34]Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao:
Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy. ISQED 2003: 327-332 - 2002
- [j8]Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1): 81-92 (2002) - [j7]Chung-Wen Albert Tsao, Cheng-Kok Koh:
UST/DME: a clock tree router for general skew constraints. ACM Trans. Design Autom. Electr. Syst. 7(3): 359-379 (2002) - [c33]Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh:
A factorization-based framework for passivity-preserving model reduction of RLC systems. DAC 2002: 40-45 - [c32]Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao:
Flip-Flop and Repeater Insertion for Early Interconnect Planning. DATE 2002: 690-695 - [c31]Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy:
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. DATE 2002: 931-935 - [c30]Guoan Zhong, Cheng-Kok Koh, Kaushik Roy:
On-chip interconnect modeling by wire duplication. ICCAD 2002: 341-346 - [c29]Guoan Zhong, Cheng-Kok Koh:
Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects. ICCD 2002: 428-433 - [c28]Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy:
Synthesis of Selectively Clocked Skewed Logic Circuits. ISQED 2002: 229-234 - [c27]Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao:
Power Supply Noise Suppression via Clock Skew Scheduling. ISQED 2002: 355-360 - [c26]Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh:
Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods. ASP-DAC/VLSI Design 2002: 311-316 - [c25]Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. ASP-DAC/VLSI Design 2002: 489- - 2001
- [j6]Probir Sarkar, Cheng-Kok Koh:
Routability-driven repeater block planning for interconnect-centricfloorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5): 660-671 (2001) - [j5]Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan:
Interconnect sizing and spacing with consideration of couplingcapacitance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9): 1164-1169 (2001) - [j4]Jason Cong, Cheng-Kok Koh, Patrick H. Madden:
Interconnect layout optimization under higher order RLC model forMCM designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(12): 1455-1463 (2001) - [c24]V. Balakrishnan, Q. Su, Cheng-Kok Koh:
Efficient balance-and-truncate model reduction for large scale systems. ACC 2001: 4746-4751 - [c23]Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. DAC 2001: 846-851 - [c22]Probir Sarkar, Cheng-Kok Koh:
Repeater block planning under simultaneous delay and transition time constraints. DATE 2001: 540-545 - [c21]Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Power trends and performance characterization of 3-dimensional integration. ISCAS (4) 2001: 414-417 - [c20]Rui Wang, Kaushik Roy, Cheng-Kok Koh:
Short-circuit power analysis of an inverter driving an RLC load. ISCAS (4) 2001: 886-889 - [c19]Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy:
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. ISLPED 2001: 267-270 - [c18]Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Decoupling capacitance allocation for power supply noise suppression. ISPD 2001: 66-71 - [c17]Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. ISQED 2001: 217-222 - [e1]Kaushik Roy, Sung-Mo Kang, Cheng-Kok Koh:
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001. ACM 2001, ISBN 1-58113-351-0 [contents] - 2000
- [c16]Liqiong Wei, Kaushik Roy, Cheng-Kok Koh:
Power minimization by simultaneous dual-Vth assignment and gate-sizing. CICC 2000: 413-416 - [c15]Cheng-Kok Koh, Patrick H. Madden:
Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures. ACM Great Lakes Symposium on VLSI 2000: 47-52 - [c14]Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. ICCAD 2000: 208-213 - [c13]Chung-Wen Albert Tsao, Cheng-Kok Koh:
UST/DME: A Clock Tree Router for General Skew Constraints. ICCAD 2000: 400-405 - [c12]Guoan Zhong, Cheng-Kok Koh, Kaushik Roy:
A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise. ICCAD 2000: 406-411 - [c11]Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Frequency Domain Analysis of Switching Noise on Power Supply Network. ICCAD 2000: 487-492 - [c10]Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. ICCD 2000: 65-72 - [c9]Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar:
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. ICCD 2000: 241-246 - [c8]Probir Sarkar, Vivek Sundararaman, Cheng-Kok Koh:
Routability-driven repeater block planning for interconnect-centric floorplanning. ISPD 2000: 186-191
1990 – 1999
- 1998
- [j3]Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing. ACM Trans. Design Autom. Electr. Syst. 3(3): 341-388 (1998) - 1997
- [c7]Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo:
Interconnect design for deep submicron ICs. ICCAD 1997: 478-485 - [c6]Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan:
Global interconnect sizing and spacing with consideration of coupling capacitance. ICCAD 1997: 628-633 - [c5]Jason Cong, Cheng-Kok Koh:
Interconnect layout optimization under higher-order RLC model. ICCAD 1997: 713-720 - 1996
- [j2]Jason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden:
Performance optimization of VLSI interconnect layout. Integr. 21(1-2): 1-94 (1996) - [c4]Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung:
Simultaneous buffer and wire sizing for performance and power optimization. ISLPED 1996: 271-276 - 1995
- [c3]Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing under Elmore delay. ICCAD 1995: 66-71 - [c2]Jason Cong, Cheng-Kok Koh:
Minimum-Cost Bounded-Skew Clock Routing. ISCAS 1995: 215-218 - 1994
- [j1]Jason Cong, Cheng-Kok Koh:
Simultaneous driver and wire sizing for performance and power optimization. IEEE Trans. Very Large Scale Integr. Syst. 2(4): 408-425 (1994) - [c1]Jason Cong, Cheng-Kok Koh:
Simultaneous driver and wire sizing for performance and power optimization. ICCAD 1994: 206-212
Coauthor Index
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