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2020 – today
- 2024
[c79]Tzu-Chuan Lin, Fang-Yu Hsu, Wai-Kei Mak, Ting-Chi Wang:
An Effective Netlist Planning Approach for Double-sided Signal Routing. ASPDAC 2024: 288-293- [c78]Yun-Kai Fang, Ye-Chih Lin, Ting-Chi Wang:
A Fast and Robust Global Router with Capacity Reduction Techniques. ASPDAC 2024: 969-974 - [c77]Wuqian Tang, Yi-Ting Li, Kai-Po Hsu, Kuan-Ling Chou, You-Cheng Lin, Chia-Feng Chien, Tzu-Li Hsu, Yung-Chih Chen, Ting-Chi Wang, Shih-Chieh Chang, TingTing Hwang, Chun-Yao Wang:
A Hybrid Approach to Reverse Engineering on Combinational Circuits. DATE 2024: 1-2 - [c76]Fang-Yu Hsu
, Tzu-Chuan Lin, Wai-Kei Mak, Ting-Chi Wang:
A Bounding Box-based Net Partitioning Method for Double-sided Routing. ACM Great Lakes Symposium on VLSI 2024: 397-402 - [c75]Ting-Chi Wang:
Pioneering Contributions of Professor Martin D. F. Wong to Automatic Floorplan Design. ISPD 2024: 229 - [c74]Zi-Hao Guo, Ting-Chi Wang:
SMT-Based Layout Synthesis Approaches for Quantum Circuits. ISPD 2024: 235-243 - [i1]Johann Knechtel, Mohammad Eslami, Peng Zou, Min Wei, Xingyu Tong, Binggang Qiu, Zhijie Cai, Guohao Chen, Benchao Zhu, Jiawei Li, Jun Yu, Jianli Chen, Chun-Wei Chiu, Min-Feng Hsieh, Chia-Hsiu Ou, Ting-Chi Wang, Bangqi Fu, Qijing Wang, Yang Sun, Qin Luo, Anthony W. H. Lau, Fangzhou Wang, Evangeline F. Y. Young, Shunyang Bi, Guangxin Guo, Haonan Wu, Zhengguang Tang, Hailong You, Cong Li, Ramesh Karri, Ozgur Sinanoglu, Samuel Pagliarini:
Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. IACR Cryptol. ePrint Arch. 2024: 1440 (2024) - 2023
- [c73]Syuan-Han Liang, Tsu-Ling Hsiung, Wai-Kei Mak, Ting-Chi Wang:
Hybrid-Row-Height Design Placement Legalization Considering Cell Variants. ACM Great Lakes Symposium on VLSI 2023: 363-367 - [c72]Chun-Wei Chiu, Yun-Kai Fang, Shao-Ting Chung, Ting-Chi Wang:
A Macro Legalization Approach Considering Minimum Channel Spacing and Buffer Area Reservation Constraints. ACM Great Lakes Symposium on VLSI 2023: 391-395 - [c71]Po-Hao Huang, Yung-Yuan Lan, Wilbert Harriman, Venesia Chiuwanara, Ting-Chi Wang:
Fast and Accurate Detection of Audio Adversarial Examples. ISCAS 2023: 1-5 - [c70]Chieh-Yu Cheng, Ting-Chi Wang:
Routability-aware Placement Guidance Generation for Mixed-size Designs. ISQED 2023: 1-7 - [c69]Zhi-Hong Lee, Chen-Han Lu, Hsin-Hung Pan, Ting-Chi Wang, Po-Yuan Chen, Cindy Chin-Fang Shen:
A Robust Routing Guide Generation Approach for Mixed-Size Designs. MLCAD 2023: 1-6 - 2022
- [j21]Po-Hao Huang, Honggang Yu, Max Panoff, Ting-Chi Wang:
Generation of Black-box Audio Adversarial Examples Based on Gradient Approximation and Autoencoders. ACM J. Emerg. Technol. Comput. Syst. 18(3): 59:1-59:19 (2022) - [j20]Genggeng Liu, Xinghai Zhang, Wenzhong Guo, Xing Huang, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang:
Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1957-1970 (2022) - [c68]Kuan-Yu Chen, Hsiu-Chu Hsu, Wai-Kei Mak, Ting-Chi Wang:
HybridGP: Global Placement for Hybrid-Row-Height Designs. ASP-DAC 2022: 294-299 - [c67]Meng-Yun Liu, Yu-Cheng Lai, Wai-Kei Mak, Ting-Chi Wang:
Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization. ICCAD 2022: 75:1-75:9 - [c66]Kuei-Huan Chang, Hsin-Hung Pan, Ting-Chi Wang, Po-Yuan Chen, Cindy Chin-Fang Shen:
On Predicting Solution Quality of Maze Routing Using Convolutional Neural Network. ISQED 2022: 1-6 - [c65]Lieqiu Jiang, Zepeng Li, Chenpeng Bao, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang:
LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction. VLSI-SoC 2022: 1-6 - [c64]Yidan Jing, Liliang Yang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang:
SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage Partition. VLSI-SoC 2022: 1-6 - 2021
- [c63]Bo-Yang Chen, Chi-Chun Fang, Wai-Kei Mak, Ting-Chi Wang:
Multiple-Layer Multiple-Patterning Aware Placement Refinement for Mixed-Cell-Height Designs. ISPD 2021: 31-38 - 2020
- [c62]Kuei-Huan Chang, Po-Hao Huang, Honggang Yu, Yier Jin, Ting-Chi Wang:
Audio Adversarial Examples Generation with Recurrent Neural Networks*. ASP-DAC 2020: 488-493 - [c61]Xinghai Zhang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Wenzhong Guo, Ting-Chi Wang:
MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes. DATE 2020: 586-591 - [c60]Da-Yu Kao, Ting-Chi Wang, Fu-Ching Tsai:
Forensic Artifacts of Network Traffic on WeChat Calls. ICACT 2020: 262-267 - [c59]Sheng-Hao Wang, Yen-Jong Chen, Ting-Chi Wang, Oscar Chen:
An Algorithm for Rule-based Layout Pattern Matching. ICCAD 2020: 33:1-33:8 - [c58]Weida Zhu, Xinghai Zhang, Genggeng Liu, Wenzhong Guo, Ting-Chi Wang:
MiniDeviation: An Efficient Multi-Stage Bus-Aware Global Router. VLSI-DAT 2020: 1-4
2010 – 2019
- 2019
- [c57]Yi-Cheng Zhao, Yu-Chieh Lin, Ting-Chi Wang, Ting-Hsiung Wang, Yun-Ru Wu, Hsin-Chang Lin, Shu-Yi Kao:
A Mixed-Height Standard Cell Placement Flow for Digital Circuit Blocks*. DATE 2019: 328-331 - [c56]Genggeng Liu, Zhen Zhuang, Wenzhong Guo, Ting-Chi Wang:
RDTA: An Efficient Routability-Driven Track Assignment Algorithm. ACM Great Lakes Symposium on VLSI 2019: 315-318 - 2018
- [c55]Yu-Hsiang Cheng, Ding-Wei Huang, Wai-Kei Mak, Ting-Chi Wang:
A practical detailed placement algorithm under multi-cell spacing constraints. ICCAD 2018: 63 - [c54]Atsushi Takahashi, Shimpei Sato, Hiroki Ogura, Yu-Min Sung, Ting-Chi Wang:
Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses. ISVLSI 2018: 494-497 - 2017
- [j19]Po-Yi Wu, Wai-Kei Mak, Ting-Chi Wang, Cheng Zhuo, Kassan Unda, Yiyu Shi:
A routing framework for technology migration with bump encroachment. Integr. 58: 1-8 (2017) - [c53]Szu-Yuan Han, Wen-Hao Liu, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang:
Delay-driven layer assignment for advanced technology nodes. ASP-DAC 2017: 456-462 - [c52]Ye-Hong Chen, Sheng-He Wang, Ting-Chi Wang:
On refining standard cell placement for self-aligned double patterning. DATE 2017: 1492-1497 - 2016
- [c51]Man-Pan Wong, Wen-Hao Liu, Ting-Chi Wang:
Negotiation-based track assignment considering local nets. ASP-DAC 2016: 378-383 - [c50]Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng:
Online slack-time binning for IO-registered die-to-die interconnects. ITC 2016: 1-8 - 2015
- [j18]Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang:
Region-Based and Panel-Based Algorithms for Unroutable Placement Recognition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 502-514 (2015) - [j17]Hsi-An Chien, Ye-Hong Chen, Szu-Yuan Han, Hsiu-Yu Lai, Ting-Chi Wang:
On Refining Row-Based Detailed Placement for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 778-793 (2015) - [c49]Hsi-An Chien, Szu-Yuan Han, Ye-Hong Chen, Ting-Chi Wang:
A Cell-Based Row-Structure Layout Decomposer for Triple Patterning Lithography. ISPD 2015: 67-74 - 2014
- [j16]Chih-Hung Liu, Chun-Xun Lin, I-Che Chen, D. T. Lee, Ting-Chi Wang:
Efficient Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Geometric Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1928-1941 (2014) - [c48]Hsi-An Chien, Ting-Chi Wang:
Redundant-via-aware ECO routing. ASP-DAC 2014: 418-423 - [c47]Wen-Hao Liu, Min-Sheng Chang, Ting-Chi Wang:
Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs. DAC 2014: 5:1-5:6 - [c46]Sergiy Popovych, Hung-Hao Lai, Chieh-Min Wang, Yih-Lang Li, Wen-Hao Liu, Ting-Chi Wang:
Density-aware Detailed Placement with Instant Legalization. DAC 2014: 122:1-122:6 - [c45]Hsi-An Chien, Zhen-Yu Peng, Yun-Ru Wu, Ting-Hsiung Wang, Hsin-Chang Lin, Chi-Feng Wu, Ting-Chi Wang:
Mask-cost-aware ECO routing∗. DATE 2014: 1-4 - [c44]Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang:
Metal layer planning for silicon interposers with consideration of routability and manufacturing cost. DATE 2014: 1-6 - [c43]Rickard Ewetz, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang, Cheng-Kok Koh:
A study on the use of parallel wiring techniques for sub-20nm designs. ACM Great Lakes Symposium on VLSI 2014: 129-134 - [c42]Wen-Hao Liu, Zhen-Yu Peng, Ting-Chi Wang:
A resource-level parallel approach for global-routing-based routing congestion estimation and a method to quantify estimation accuracy. ICCAD 2014: 389-396 - [c41]Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang:
A study on unroutable placement recognition. ISPD 2014: 19-26 - 2013
- [j15]Cha-Ru Li, Wai-Kei Mak, Ting-Chi Wang:
Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 523-532 (2013) - [c40]Bo-Han Zeng, Ren-Song Tsay, Ting-Chi Wang:
An efficient hybrid synchronization technique for scalable multi-core instruction set simulations. ASP-DAC 2013: 588-593 - 2012
- [j14]Wai-Kei Mak, Yu-Chen Lin, Chris Chu, Ting-Chi Wang:
Pad Assignment for Die-Stacking System-in-Package Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(11): 1711-1722 (2012) - 2011
- [j13]Ming-Chao Tsai, Ting-Chi Wang, Ting Ting Hwang:
Through-Silicon Via Planning in 3-D Floorplanning. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1448-1457 (2011) - [c39]Shing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao:
Simultaneous redundant via insertion and line end extension for yield optimization. ASP-DAC 2011: 633-638 - [c38]Tsung-Hsien Lee, Yen-Jung Chang, Ting-Chi Wang:
An enhanced global router with consideration of general layer directives. ISPD 2011: 53-60 - 2010
- [j12]Kuang-Yao Lee, Shing-Tung Lin, Ting-Chi Wang:
Enhanced Double Via Insertion Using Wire Bending. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 171-184 (2010) - [j11]Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao:
Optimal Double Via Insertion With On-Track Preference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 318-323 (2010) - [j10]Yen-Jung Chang, Yu-Ting Lee, Jhih-Rong Gao, Pei-Ci Wu, Ting-Chi Wang:
NTHU-Route 2.0: A Robust Global Router for Modern Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 1931-1944 (2010) - [c37]De-Yu Liu, Wai-Kei Mak, Ting-Chi Wang:
Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design. ACM Great Lakes Symposium on VLSI 2010: 423-428 - [c36]Tsung-Hsien Lee, Ting-Chi Wang:
Simultaneous antenna avoidance and via optimization in layer assignment of multi-layer global routing. ICCAD 2010: 312-318 - [c35]Yen-Jung Chang, Tsung-Hsien Lee, Ting-Chi Wang:
GLADE: A modern global router considering layer directives. ICCAD 2010: 319-323
2000 – 2009
- 2009
- [c34]Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang:
Pad assignment for die-stacking System-in-Package design. ICCAD 2009: 249-255 - [c33]Kuang-Yao Lee, Shing-Tung Lin, Ting-Chi Wang:
Redundant via insertion with wire bending. ISPD 2009: 123-130 - [c32]Tsung-Hsien Lee, Ting-Chi Wang:
Robust layer assignment for via optimization in multi-layer global routing. ISPD 2009: 159-166 - 2008
- [j9]Tsung-Hsien Lee, Ting-Chi Wang:
Congestion-Constrained Layer Assignment for Via Minimization in Global Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1643-1656 (2008) - [j8]Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao:
Fast and Optimal Redundant Via Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2197-2208 (2008) - [c31]Jhih-Rong Gao, Pei-Ci Wu, Ting-Chi Wang:
A new global router for modern designs. ASP-DAC 2008: 232-237 - [c30]Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang:
An MILP-based wire spreading algorithm for PSM-aware layout modification. ASP-DAC 2008: 364-369 - [c29]Tien-Yuan Hsu, Ting-Chi Wang:
A generalized network flow based algorithm for power-aware FPGA memory mapping. DAC 2008: 30-33 - [c28]Yen-Jung Chang, Yu-Ting Lee, Ting-Chi Wang:
NTHU-Route 2.0: a fast and stable global router. ICCAD 2008: 338-343 - [c27]Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao:
Optimal post-routing redundant via insertion. ISPD 2008: 111-117 - [r1]Ting-Chi Wang, Martin D. F. Wong:
Slicing Floorplans. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [c26]Chung-Wei Lin, Ming-Chao Tsai, Kuang-Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang:
Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. ASP-DAC 2007: 238-243 - [c25]Pei-Ci Wu, Jhih-Rong Gao, Ting-Chi Wang:
A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction. ASP-DAC 2007: 262-267 - [c24]Tien-Ting Fang, Ting-Chi Wang:
Fast Buffered Delay Estimation Considering Process Variations. ASP-DAC 2007: 702-707 - 2006
- [c23]Kuang-Yao Lee, Ting-Chi Wang:
Post-routing redundant via insertion for yield/reliability improvement. ASP-DAC 2006: 303-308 - [c22]Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao:
Post-routing redundant via insertion and line end extension with via density consideration. ICCAD 2006: 633-640 - 2005
- [c21]Zhong-Ching Lu, Ting-Chi Wang:
Concurrent flip-flop and buffer insertion with adaptive blockage avoidance. ASP-DAC 2005: 19-22 - [c20]Yun-Ru Wu, Ming-Chao Tsai, Ting-Chi Wang:
Maze routing with OPC consideration. ASP-DAC 2005: 198-203 - [c19]Hao-Yueh Hsieh, Ting-Chi Wang:
Simple yet effective algorithms for block and I/O buffer placement in flip-chip design. ISCAS (2) 2005: 1879-1882 - 2004
- [j7]Cliff C. N. Sze, Ting-Chi Wang, Li-C. Wang:
Multilevel circuit clustering for delay minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 1073-1085 (2004) - 2003
- [j6]Cliff C. N. Sze, Ting-Chi Wang:
Optimal circuit clustering for delay minimization under a more general delay model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 646-651 (2003) - [c18]Chin Ngai Sze, Ting-Chi Wang:
Performance-driven multi-level clustering for combinational circuits. ASP-DAC 2003: 729-740 - 2002
- [c17]S. Dhamdhere, Ningyu Zhou, Ting-Chi Wang:
Module placement with pre-placed modules using the corner block list representation. ISCAS (1) 2002: 349-352 - [c16]Cliff C. N. Sze, Ting-Chi Wang:
Optimal circuit clustering with variable interconnect delay. ISCAS (4) 2002: 707-710 - [c15]Cliff C. N. Sze, Ting-Chi Wang:
Multi-Level Circuit Clustering for Delay Minimization. IWLS 2002: 227-232 - 2001
- [c14]Jianbang Lai, Ming-Shiun Lin, Ting-Chi Wang, Li-C. Wang:
Module placement with boundary constraints using the sequence-pair representation. ASP-DAC 2001: 515-520 - [c13]Zhi-Hong Wang, En-Cheng Liu, Jianbang Lai, Ting-Chi Wang:
Power minization in LUT-based FPGA technology mapping. ASP-DAC 2001: 635-640 - [c12]Yi-He Jiang, Jianbang Lai, Ting-Chi Wang:
Module placement with pre-placed modules using the B*-tree representation. ISCAS (5) 2001: 347-350 - [c11]En-Cheng Liu, Ming-Shiun Lin, Jianbang Lai, Ting-Chi Wang:
Slicing floorplan design with boundary-constrained modules. ISPD 2001: 124-129 - 2000
- [c10]Hsun-Cheng Lee, Ting-Chi Wang:
Feasible two-way circuit partitioning with complex resource constraints. ASP-DAC 2000: 435-440 - [c9]Jennifer Dworak, Michael R. Grimaila, Brad Cobb, Ting-Chi Wang, Li-C. Wang, M. Ray Mercer:
On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction. Asian Test Symposium 2000: 151- - [c8]En-Cheng Liu, Tu-Hsing Lin, Ting-Chi Wang:
On accelerating slicing floorplan design with boundary constraints. ISCAS 2000: 399-402
1990 – 1999
- 1999
- [c7]Jan-Yang Chang, Yu-Chen Liu, Ting-Chi Wang:
Faster and Better Spectral Algorithms for Multi-Way Partitioning. ASP-DAC 1999: 81- - 1997
- [j5]Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu:
Routing for symmetric FPGAs and FPICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1): 20-31 (1997) - 1995
- [j4]Ting-Chi Wang, Martin D. F. Wong, Yachyang Sun, Chak-Kuen Wong:
Optimal net assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2): 265-269 (1995) - [j3]T. W. Her, Ting-Chi Wang, Martin D. F. Wong:
Performance-driven channel pin assignment algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(7): 849-857 (1995) - 1993
- [j2]Ting-Chi Wang, D. F. Wong:
Graph-based techniques to speed up floorplan area optimization. Integr. 15(2): 179-199 (1993) - [c6]Ting-Chi Wang, D. F. Wong, Yachyang Sun, C. K. Wong:
On over-the-cell channel routing. EURO-DAC 1993: 110-115 - [c5]Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu:
Routing for symmetric FPGAs and FPICs. ICCAD 1993: 486-490 - [c4]Yao-Ping Chen, Ting-Chi Wang, D. F. Wong:
A Graph Partitioning Problem for Multiple-chip Design. ISCAS 1993: 1778-1781 - [p1]Ting-Chi Wang, D. F. Wong:
A note on the Complexity of Stockmeyer's floorplan Optimization Technique. Algorithmic Aspects of VLSI Layout 1993: 309-320 - 1992
- [j1]Ting-Chi Wang, Martin D. F. Wong:
Optimal floorplan area optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(8): 992-1002 (1992) - [c3]Ting-Chi Wang, D. F. Wong:
A Graph Theoretic Technique to Speed up Floorplan Area Optimization. DAC 1992: 62-68 - 1991
- [c2]Ting-Chi Wang, D. F. Wong:
Efficient shape curve construction in floorplan design. EURO-DAC 1991: 356-360 - 1990
- [c1]Ting-Chi Wang, D. F. Wong:
An Optimal Algorithm for Floorplan Area Optimization. DAC 1990: 180-186
Coauthor Index
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