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2020 – today
- 2024
[j7]Jahoon Jin
, Soo-Min Lee, Kyunghwan Min, Sodam Ju, Jihoon Lim, Jisu Yook, Jihoon Lee, Hyunsu Chae, Kwonwoo Kang, Yunji Hong, Yeongcheol Jeong, Sungsik Park, Sang-Ho Kim, Jongwoo Lee, Joonsuk Kim, Sung-Ung Kwak:
A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization. IEEE J. Solid State Circuits 59(1): 184-195 (2024)- [c9]Kyunghwan Min, Jahoon Jin, Soo-Min Lee, Sodam Ju, Jisu Yook, Jihoon Lee, Yunji Hong, Sungsik Park, Sang-Ho Kim, Jongwoo Lee, Hyungjong Ko:
A 20Gb/s/pin Single-Ended PAM-4 Transceiver with Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing for Low-Power Memory Interfaces. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c8]Jahoon Jin, Soo-Min Lee, Kyunghwan Min, Sodam Ju, Jihoon Lim, Hyunsu Chae, Kwonwoo Kang, Yunji Hong, Yeongcheol Jeong, Sang-Ho Kim, Jongwoo Lee, Joonsuk Kim:
A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization. ISSCC 2023: 404-405 - 2022
- [c7]Soo-Min Lee, Jihoon Lim, Jaehyuk Jang, Hyoungjoong Kim, Kyunghwan Min, Woongki Min, Hyeonji Han, Gyusik Kim, Jaeyoung Kim, Chulho Kim, Sejun Jeon, Jinhoon Park, Hyunsu Chae, Sangwook Han, Hiep Pham, Xingliang Zhao, Qilin Gu, Chih-Wei Yao, Sangho Kim, Jongwoo Lee:
A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET. ESSCIRC 2022: 509-512 - 2020
- [c6]Soo-Min Lee, Kihwan Seong, Joohee Shin, Hyoungjoong Kim, Jaehyun Jeong, Shinyoung Yi, Juyoung Kim, Eunsu Kim, Sukhyun Jung, Sangyun Hwang, Jihun Oh, Kwanyeob Chae, Kyounghoi Koo, Sanghune Park, Jongshin Shin, Jaehong Park:
22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique. ISSCC 2020: 338-340
2010 – 2019
- 2019
- [c5]Kwanyeob Chae, JongRyun Choi, Hyungkwon Lee, Jinho Choi, Shinyoung Yi, Yoonjee Nam, Sangyun Hwang, Joohyung Lee, Won Lee, Kihwan Seong, Joohee Shin, Soo-Min Lee, Seokkyun Ko, Jihun Oh, Billy Koo, Sanghune Park, Jongshin Shin, Hyungjong Ko:
An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme. VLSI Circuits 2019: 96- - 2017
- [c4]Soo-Min Lee, Jihun Oh, Jinho Choi, Seokkyun Ko, Daero Kim, Kyounghoi Koo, JongRyun Choi, Yoonjee Nam, Sangsoo Park, Hyungkweon Lee, Eunsu Kim, Sukhyun Jung, Kwanyeob Chae, SuHo Kim, Sanghune Park, Sanghyun Lee, Sungho Park:
23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller. ISSCC 2017: 398-399 - 2016
- [j6]Soo-Min Lee, Ji-Hoon Lim, Il-Min Yi, Young Jae Jang, Hae-Kang Jung, Kyunghoon Kim, Dae-Han Kwon, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface. IEEE J. Solid State Circuits 51(8): 1890-1901 (2016) - [j5]Il-Min Yi, Soo-Min Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(1): 122-133 (2016) - [c3]Il-Min Yi, Seung-Jun Bae, Min-Kyun Chae, Soo-Min Lee, Young Jae Jang, Young-Chul Cho, Young-Soo Sohn, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme. VLSI Circuits 2016: 1-2 - 2014
- [j4]Soo-Min Lee, Il-Min Yi, Hae-Kang Jung, Hyunbae Lee, Yong-Ju Kim, Yunsaing Kim, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface. IEEE J. Solid State Circuits 49(11): 2618-2630 (2014) - [j3]Il-Min Yi, Soo-Min Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Hwan Choi, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination. IEEE Trans. Circuits Syst. II Express Briefs 61-II(12): 987-991 (2014) - 2013
- [c2]Soo-Min Lee, Jong-Hoon Kim, Jong-Sam Kim, Yunsaing Kim, Hyunbae Lee, Jae-Yoon Sim, Hong-June Park:
A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX. ISSCC 2013: 308-309 - 2012
- [j2]Hae-Kang Jung, Il-Min Yi, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park:
A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines. IEEE J. Solid State Circuits 47(9): 2068-2079 (2012) - 2011
- [j1]Hyung-Joon Chi, Young-Ho Choi, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park, Jong-Jin Lim, Pil-Sung Kang, Bu-Yeol Lee, Jin-Cheol Hong, Hee-Sub Lee:
A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL. IEEE Trans. Circuits Syst. II Express Briefs 58-II(10): 687-691 (2011) - 2010
- [c1]Hae-Kang Jung, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park:
A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines. CICC 2010: 1-4
Coauthor Index
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