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ORCIDFarshid Aryanfar
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2010 – 2019
- 2017
[j6]Anirban Sarkar
, Farshid Aryanfar, Brian A. Floyd:
A 28-GHz SiGe BiCMOS PA With 32% Efficiency and 23-dBm Output Power. IEEE J. Solid State Circuits 52(6): 1680-1686 (2017)- 2015
- [j5]Mohammad Hekmat, Farshid Aryanfar, Jason Wei, Vijay P. Gadde, Reza Navid:
A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators. IEEE J. Solid State Circuits 50(2): 490-502 (2015) - 2014
- [j4]Wonil Roh, Ji-Yun Seol, Jeongho Park, Byunghwan Lee, Jaekon Lee, Yungsoo Kim, Jaeweon Cho, Kyungwhoon Cheun, Farshid Aryanfar:
Millimeter-wave beamforming as an enabling technology for 5G cellular communications: theoretical feasibility and prototype results. IEEE Commun. Mag. 52(2): 106-113 (2014) - 2013
- [j3]Jing-Hwa Chen, S. R. Helmi, R. Azadegan, Farshid Aryanfar, S. Mohammadi:
A Broadband Stacked Power Amplifier in 45-nm CMOS SOI Technology. IEEE J. Solid State Circuits 48(11): 2775-2784 (2013) - 2011
- [j2]Shreyas Sen, Farshid Aryanfar, Carl W. Werner:
A Multiband Transceiver System in 45-nm CMOS for Extended Data Rate through Notchy Wireline Channels. IEEE Trans. Circuits Syst. II Express Briefs 58-II(9): 545-549 (2011) - 2010
- [j1]Farshid Aryanfar, Amir Amirkhany:
A Low-Cost Resonance Mitigation Technique for Multidrop Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 57-II(5): 339-342 (2010) - [c1]Ting Wu, Farshid Aryanfar, Haechang Lee, Jie Shen, T. J. Chin, Carl W. Werner, Ken Chang:
Low-skew clock distribution using zero-phase-clock-buffer DLLs. ISSCC 2010: 176-177
Coauthor Index
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