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2020 – today
- 2020
[c10]Yi-An Chen, Gung-Yu Pan, Che-Hua Shih, Yen-Chin Liao, Chia-Chih Yen, Hsie-Chia Chang:
Embedding Hierarchical Signal to Siamese Network for Fast Name Rectification. DATE 2020: 891-896
2010 – 2019
- 2019
- [c9]Chia-Chih Jack Yen:
Failure Root Cause Analysis Automation on Functional Simulation Regressions. VLSI-DAT 2019: 1 - 2014
- [j4]An-Che Cheng, Chia-Chih Jack Yen, Celina G. Val, Sam Bayless, Alan J. Hu, Iris Hui-Ru Jiang, Jing-Yang Jou:
Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog. ACM Trans. Design Autom. Electr. Syst. 20(1): 7:1-7:23 (2014) - 2012
- [c8]An-Che Cheng, Chia-Chih Yen, Jing-Yang Jou:
A formal method to improve SystemVerilog functional coverage. HLDVT 2012: 56-63 - 2010
- [j3]Che-Hua Shih, Ya-Ching Yang, Chia-Chih Yen, Juinn-Dar Huang, Jing-Yang Jou:
FSM-Based Formal Compliance Verification of Interface Protocols. J. Inf. Sci. Eng. 26(5): 1601-1617 (2010)
2000 – 2009
- 2008
- [c7]Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu:
A General Failure Candidate Ranking Framework for Silicon Debug. VTS 2008: 352-358 - 2006
- [j2]Chia-Chih Yen, Jing-Yang Jou:
An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging. IEEE Trans. Computers 55(11): 1356-1366 (2006) - [c6]Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu:
Diagnosing Silicon Failures Based on Functional Test Patterns. MTV 2006: 94-98 - 2005
- [c5]Chia-Chih Yen, Jing-Yang Jou:
An optimum algorithm for compacting error traces for efficient functional debugging. HLDVT 2005: 177-183 - 2004
- [j1]Chia-Chih Yen, Jing-Yang Jou, Kuang-Chien Chen:
A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation. IEEE Des. Test Comput. 21(2): 111-120 (2004) - [c4]Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou:
On compliance test of on-chip bus for SOC. ASP-DAC 2004: 328-333 - [c3]Chia-Chih Yen, Jing-Yang Jou:
Enhancing sequential depth computation with a branch-and-bound algorithm. HLDVT 2004: 3-8 - 2002
- [c2]Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou:
A Practical Approach to Cycle Bound Estimation for Property Checking. IWLS 2002: 149-154 - 2001
- [c1]Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou:
Automatic Functional Vector Generation Using the Interacting FSM Model. ISQED 2001: 372-377
Coauthor Index
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