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2020 – today
- 2021
[j3]Pascal Vivet
, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy:
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. IEEE J. Solid State Circuits 56(1): 79-97 (2021)- 2020
- [c20]Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy:
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. ISSCC 2020: 46-48
2010 – 2019
- 2018
- [c19]Lucile Arnaud, Stéphane Moreau, Amadine Jouve, Imed Jani, Didier Lattard, F. Fournel, C. Euvrard, Y. Exbrayat, Viorel Balan, Nicolas Bresson, S. Lhostis, J. Jourdon, E. Deloffre, S. Guillaumet, Alexis Farcy, Simon Gousseau, M. Arnoux:
Fine pitch 3D interconnections with hybrid bonding technology: From process robustness to reliability. IRPS 2018: 4 - 2016
- [j2]Perceval Coudrain, Papa Momar Souare, Rafael Prieto, Vincent Fiori, Alexis Farcy, Laurent Le Pailleur, Jean-Philippe Colonna, Cristiano Santos, Pascal Vivet, M. Haykel Ben Jamaa, Denis Dutoit, François de Crecy, Sylvain Dumas, Christian Chancel, Didier Lattard, Séverine Cheramy:
Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits. IEEE Des. Test 33(3): 21-36 (2016) - [c18]Didier Lattard, Lucile Arnaud, Arnaud Garnier, Nicolas Bresson, Franck Bana, R. Segaud, Amadine Jouve, H. Jacquinot, Stéphane Moreau, Karim Azizi-Mourier, C. Chantre, Pascal Vivet, Gaël Pillonnet, F. Casset, F. Ponthenier, Alexis Farcy, S. Lhostis, Jean Michailos, Alexandre Arriordaz, Séverine Cheramy:
ITAC: A complete 3D integration test platform. 3DIC 2016: 1-4 - [c17]Rafael Prieto, Perceval Coudrain, Jean-Philippe Colonna, Y. Hallez, Christian Chancel, Venceslass Rat, Sylvain Dumas, G. Romano, R. Franiatte, C. Brunet-Manquiat, Séverine Cheramy, Alexis Farcy:
Heat spreading packaging solutions for hybrid bonded 3D-ICs. 3DIC 2016: 1-6 - 2015
- [j1]Simon Gousseau, Stéphane Moreau, David Bouchu, Alexis Farcy, Pierre Montmitonnet, Karim Inal, François Bay, Marc Zelsmann, Emmanuel Picard, Mathieu Salaün:
Electromigration-induced failure in operando characterization of 3D interconnects: microstructure influence. Microelectron. Reliab. 55(8): 1205-1213 (2015) - [c16]Benjamin Vianne, Alexis Farcy, Vincent Fiori, Cédrick Chappaz, Norbert Chevrier, G. Lobascio, Pascal Chausse, F. Ponthenier, A. Ruckly, Stephanie Escoubas, Olivier Thomas:
Stress management strategy to limit die curvature during silicon interposer integration. 3DIC 2015: TS11.4.1-TS11.4.7 - [c15]Frédéric Boeuf, Sebastien Cremer, Enrico Temporiti, Massimo Fere, Mark Shaw, Nathalie Vulliet, Bastien Orlando, Delia Ristoiu, Alexis Farcy, Thierry Pinguet, Attila Mekis, Gianlorenzo Masini, Peng Sun, Yuemeng Chi, Herve Petiton, Sebastien Jan, Jean-Robert Manouvrier, Charles Baudot, Patrick Le Maitre, Jean Francois Carpentier, Laurent Salager, Matteo Traldi, Luca Maggi, Danilo Rigamonti, Chiara Zaccherini, Carolina Elemi, Bernard Sautreuil, Luigi Verga:
Recent progress in Silicon Photonics R&D and manufacturing on 300mm wafer platform. OFC 2015: 1-3 - 2014
- [c14]Khadim Dieng, Philippe Artillan, Cédric Bermond, Olivier Guiller, Thierry Lacrevaz, Sylvain Joblot, Gregory Houzet, Alexis Farcy, Yann Lamy, Bernard Fléchet:
Electrical model and characterization of Through Silicon Capacitors (TSC) in silicon interposer. 3DIC 2014: 1-8 - [c13]Cristiano Santos, Papa Momar Souare, François de Crecy, Perceval Coudrain, Jean-Philippe Colonna, Pascal Vivet, Andras Borbely, Ricardo Reis, M. Haykel Ben Jamaa, Vincent Fiori, Alexis Farcy:
Using TSVs for thermal mitigation in 3D circuits: Wish and truth. 3DIC 2014: 1-8 - [c12]Yves Durand, Paul M. Carpenter, Stefano Adami, Angelos Bilas, Denis Dutoit, Alexis Farcy, Georgi Gaydadjiev, John Goodacre, Manolis Katevenis, Manolis Marazakis, Emil Matús, Iakovos Mavroidis, John Thomson:
EUROSERVER: Energy Efficient Node for European Micro-Servers. DSD 2014: 206-213 - 2013
- [c11]Melanie Brocard, Cédric Bermond, Thierry Lacrevaz, Alexis Farcy, Patrick Le Maitre, P. Scheer, Patrick Leduc, Séverine Cheramy, Bernard Fléchet:
RF characterization of substrate coupling between TSV and MOS transistors in 3D integrated circuits. 3DIC 2013: 1-8 - [c10]Sylvain Joblot, Alexis Farcy, Nicolas Hotellier, Amadine Jouve, François de Crecy, Arnaud Garnier, M. Argoud, C. Ferrandon, J.-P. Colonna, R. Franiatte, C. Laviron, Séverine Cheramy:
Wafer level encapsulated materials evaluation for chip on wafer (CoW) approach in 2.5D Si interposer integration. 3DIC 2013: 1-7 - [c9]Papa Momar Souare, François de Crecy, Vincent Fiori, M. Haykel Ben Jamaa, Alexis Farcy, Sébastien Gallois-Garreignot, Andras Borbely, Jean-Philippe Colonna, Perceval Coudrain, B. Giraud, C. Laviron, Séverine Cheramy, Clément Tavernier, Jean Michailos:
Thermal correlation between measurements and FEM simulations in 3D ICs. 3DIC 2013: 1-6 - [c8]Benjamin Vianne, Pierre Bar, Vincent Fiori, Sebastien Petitdidier, Norbert Chevrier, Sébastien Gallois-Garreignot, Alexis Farcy, Pascal Chausse, Stephanie Escoubas, Nicolas Hotellier, Olivier Thomas:
Thermo-mechanical study of a 2.5D passive silicon interposer technology: Experimental, numerical and In-Situ stress sensors developments. 3DIC 2013: 1-7 - 2012
- [c7]Patrick Le Maitre, Melanie Brocard, Alexis Farcy, Jean-Claude Marin:
Device and electromagnetic co-simulation of TSV: Substrate noise study and compact modeling of a TSV in a matrix. ISQED 2012: 404-411 - 2011
- [c6]G. Druais, Pascal Ancey, C. Aumont, V. Caubet, Laurent-Luc Chapelon, C. Chaton, Séverine Cheramy, S. Cordova, E. Cirot, Jean-Philippe Colonna, Perceval Coudrain, T. Divel, Y. Dodo, Alexis Farcy, N. Guitard, K. Haxaire, Nicolas Hotellier, F. Leverd, R. Liou, Jean Michailos, A. Ostrovsky, Sebastien Petitdidier, J. Pruvost, D. Riquet, O. Robin, E. Saugier, Nicolas Sillon:
3D integration demonstration of a wireless product with design partitioning. 3DIC 2011: 1-5
2000 – 2009
- 2009
- [c5]Lionel Cadix, Alexis Farcy, Cédric Bermond, Christine Fuchs, Patrick Leduc, Maxime Rousseau, Myriam Assous, Alexandre Valentian, Julie Roullard, Elie Eid, Nicolas Sillon, Bernard Fléchet, Pascal Ancey:
Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits. 3DIC 2009: 1-7 - [c4]Elie Eid, Thierry Lacrevaz, Sébastien de Rivaz, Cédric Bermond, Bernard Fléchet, Françis Calmon, Christian Gontrand, Alexis Farcy, Lionel Cadix, Pascal Ancey:
Predictive High Frequency effects of substrate coupling in 3D integrated circuits stacking. 3DIC 2009: 1-6 - [c3]Patrick Leduc, Myriam Assous, Léa Di Cioccio, Marc Zussy, Thomas Signamarcheix, Antonio Roman, Maxime Rousseau, Sophie Verrun, Laurent Bally, David Bouchu, Lionel Cadix, Alexis Farcy, Nicolas Sillon:
First integration of Cu TSV using die-to-wafer direct bonding and planarization. 3DIC 2009: 1-5 - [c2]Julie Roullard, Stéphane Capraro, Thierry Lacrevaz, Lionel Cadix, Elie Eid, Alexis Farcy, Bernard Fléchet:
Influence of 3D integration on 2D interconnections and 2D self inductors HF properties. 3DIC 2009: 1-6 - 2008
- [c1]Manuel Sellier, Jean-Michel Portal, Bertrand Borot, Steve Colquhoun, Richard Ferrant, Frédéric Boeuf, Alexis Farcy:
Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework. ISQED 2008: 492-497
Coauthor Index
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