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ORCIDLuan H. K. Duong
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2020 – today
- 2023
[j18]Shien Zhu
, Luan H. K. Duong, Hui Chen, Di Liu, Weichen Liu:
FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3): 781-794 (2023)- 2022
- [j17]Hui Chen, Peng Chen, Jun Zhou, Luan H. K. Duong, Weichen Liu:
ArSMART: An Improved SMART NoC Design Supporting Arbitrary-Turn Transmission. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1316-1329 (2022) - [j16]Shien Zhu, Luan H. K. Duong, Weichen Liu:
TAB: Unified and Optimized Ternary, Binary, and Mixed-precision Neural Network Inference on the Edge. ACM Trans. Embed. Comput. Syst. 21(5): 50:1-50:26 (2022) - [i2]Shien Zhu, Luan H. K. Duong, Hui Chen, Di Liu, Weichen Liu:
FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks. CoRR abs/2201.07634 (2022) - 2021
- [j15]Mengquan Li, Weichen Liu, Luan H. K. Duong, Peng Chen, Lei Yang, Chunhua Xiao:
Contention-Aware Routing for Thermal-Reliable Optical Networks-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(2): 260-273 (2021) - 2020
- [j14]Xuanqi Chen, Zhifei Wang, Yi-Shing Chang, Jiang Xu, Jun Feng, Peng Yang, Zhehui Wang, Luan H. K. Duong:
Modeling and Analysis of Optical Modulators Based on Free-Carrier Plasma Dispersion Effect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(5): 977-990 (2020) - [j13]Pengxing Guo, Weigang Hou, Lei Guo, Wei Sun, Chuang Liu, Hainan Bao, Luan H. K. Duong, Weichen Liu:
Fault-Tolerant Routing Mechanism in 3D Optical Network-on-Chip Based on Node Reuse. IEEE Trans. Parallel Distributed Syst. 31(3): 547-564 (2020) - [c12]Xiangzhong Luo, Luan H. K. Duong, Weichen Liu:
Person Re-Identification Via Pose-Aware Multi-Semantic Learning. ICME 2020: 1-6 - [c11]Shien Zhu, Luan H. K. Duong, Weichen Liu:
XOR-Net: An Efficient Computation Pipeline for Binary Neural Network Inference on Edge Devices. ICPADS 2020: 124-131 - [i1]Hui Chen, Peng Chen, Jun Zhou, Luan H. K. Duong, Weichen Liu:
ArSMART: An Improved SMART NoC Design Supporting Arbitrary-Turn Transmission. CoRR abs/2011.09261 (2020)
2010 – 2019
- 2019
- [j12]Luan H. K. Duong, Peng Yang, Zhifei Wang, Yi-Shing Chang, Jiang Xu, Zhehui Wang, Xuanqi Chen:
Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(1): 43-56 (2019) - 2018
- [c10]Peng Yang, Zhengbin Pang, Zhifei Wang, Zhehui Wang, Min Xie, Xuanqi Chen, Luan H. K. Duong, Jiang Xu:
RSON: An inter/intra-chip silicon photonic network for rack-scale computing systems. DATE 2018: 1369-1374 - [c9]Xuanqi Chen, Zhifei Wang, Yi-Shing Chang, Jiang Xu, Peng Yang, Zhehui Wang, Luan H. K. Duong:
A Comprehensive Electro-Optical Model for Silicon Photonic Switches. ISVLSI 2018: 76-81 - 2017
- [j11]Haoran Li, Xuan Wang, Jiang Xu, Zhe Wang, Rafael K. V. Maeda, Zhehui Wang, Peng Yang, Luan H. K. Duong, Zhifei Wang:
Energy-Efficient Power Delivery System Paradigms for Many-Core Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(3): 449-462 (2017) - [c8]Zhe Wang, Zhongyuan Tian, Jiang Xu, Rafael K. V. Maeda, Haoran Li, Peng Yang, Zhehui Wang, Luan H. K. Duong, Zhifei Wang, Xuanqi Chen:
Modular reinforcement learning for self-adaptive energy efficiency optimization in multicore system. ASP-DAC 2017: 684-689 - [c7]Zhehui Wang, Zhengbin Pang, Peng Yang, Jiang Xu, Xuanqi Chen, Rafael K. V. Maeda, Zhifei Wang, Luan H. K. Duong, Haoran Li, Zhe Wang:
MOCA: an Inter/Intra-Chip Optical Network for Memory. DAC 2017: 86:1-86:6 - 2016
- [j10]Xuan Wang, Jiang Xu, Zhe Wang, Haoran Li, Peng Yang, Luan H. K. Duong, Rafael K. V. Maeda, Zhifei Wang:
Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign. ACM J. Emerg. Technol. Comput. Syst. 13(2): 19:1-19:24 (2016) - [j9]Zhehui Wang, Jiang Xu, Peng Yang, Xuan Wang, Zhe Wang, Luan Huu Kinh Duong, Zhifei Wang, Rafael Kioji Vivas Maeda, Haoran Li:
Improve Chip Pin Performance Using Optical Interconnects. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1574-1587 (2016) - [j8]Zhehui Wang, Jiang Xu, Peng Yang, Luan Huu Kinh Duong, Zhifei Wang, Xuan Wang, Zhe Wang, Haoran Li, Rafael Kioji Vivas Maeda:
A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2462-2474 (2016) - [j7]Luan H. K. Duong, Zhehui Wang, Mahdi Nikdast, Jiang Xu, Peng Yang, Zhifei Wang, Zhe Wang, Rafael K. V. Maeda, Haoran Li, Xuan Wang, Sébastien Le Beux, Yvain Thonnart:
Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2475-2487 (2016) - [j6]Zhe Wang, Xuan Wang, Jiang Xu, Haoran Li, Rafael K. V. Maeda, Zhehui Wang, Peng Yang, Luan H. K. Duong, Zhifei Wang:
An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3373-3386 (2016) - [c6]Rafael K. V. Maeda, Peng Yang, Xiaowen Wu, Zhe Wang, Jiang Xu, Zhehui Wang, Haoran Li, Luan H. K. Duong, Zhifei Wang:
JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models. AISTECS@HiPEAC 2016: 8:1-8:6 - [c5]Peng Yang, Shigeru Nakamura, Kenichiro Yashiki, Zhehui Wang, Luan H. K. Duong, Zhifei Wang, Xuanqi Chen, Yuichi Nakamura, Jiang Xu:
Inter/intra-chip optical interconnection network: opportunities, challenges, and implementations. NOCS 2016: 1-8 - 2015
- [j5]Xuan Wang, Jiang Xu, Zhe Wang, Kevin J. Chen, Xiaowen Wu, Zhehui Wang, Peng Yang, Luan H. K. Duong:
An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(9): 1401-1414 (2015) - [j4]Mahdi Nikdast, Jiang Xu, Luan H. K. Duong, Xiaowen Wu, Zhehui Wang, Xuan Wang, Zhe Wang:
Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 156-169 (2015) - [j3]Mahdi Nikdast, Jiang Xu, Luan Huu Kinh Duong, Xiaowen Wu, Xuan Wang, Zhehui Wang, Zhe Wang, Peng Yang, Yaoyao Ye, Qinfen Hao:
Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2552-2565 (2015) - [c4]Zhehui Wang, Jiang Xu, Peng Yang, Xuan Wang, Zhe Wang, Luan H. K. Duong, Zhifei Wang, Haoran Li, Rafael Kioji Vivas Maeda, Xiaowen Wu, Yaoyao Ye, Qinfen Hao:
Alleviate chip I/O pin constraints for multicore processors through optical interconnects. ASP-DAC 2015: 791-796 - [c3]Zhe Wang, Xuan Wang, Jiang Xu, Xiaowen Wu, Zhehui Wang, Peng Yang, Luan H. K. Duong, Haoran Li, Rafael Kioji Vivas Maeda, Zhifei Wang:
Adaptively tolerate power-gating-induced power/ground noise under process variations. DATE 2015: 483-488 - [c2]Luan H. K. Duong, Mahdi Nikdast, Jiang Xu, Zhehui Wang, Yvain Thonnart, Sébastien Le Beux, Peng Yang, Xiaowen Wu, Zhifei Wang:
Coherent crosstalk noise analyses in ring-based optical interconnects. DATE 2015: 501-506 - 2014
- [j2]Luan H. K. Duong, Mahdi Nikdast, Sébastien Le Beux, Jiang Xu, Xiaowen Wu, Zhehui Wang, Peng Yang:
A Case Study of Signal-to-Noise Ratio in Ring-Based Optical Networks-on-Chip. IEEE Des. Test 31(5): 55-65 (2014) - [j1]Yaoyao Ye, Zhehui Wang, Peng Yang, Jiang Xu, Xiaowen Wu, Xuan Wang, Mahdi Nikdast, Zhe Wang, Luan H. K. Duong:
System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(11): 1718-1731 (2014) - [c1]Mahdi Nikdast, Luan H. K. Duong, Jiang Xu, Sébastien Le Beux, Xiaowen Wu, Zhehui Wang, Peng Yang, Yaoyao Ye:
CLAP: a crosstalk and loss analysis platform for optical interconnects. NOCS 2014: 172-173
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