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ORCIDTakeshi Nagai
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2000 – 2009
- 2008
[c2]Mariko Kaku, Hitoshi Iwai, Takeshi Nagai, Masaharu Wada, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Takayuki Iwai, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano, Nobuaki Otsuka:
An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications. ISSCC 2008: 276-277- 2006
- [c1]Takeshi Nagai, Masaharu Wada, Hitoshi Iwai, Mariko Kaku, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano:
A 65nm low-power embedded DRAM with extended data-retention sleep mode. ISSCC 2006: 567-576
1990 – 1999
- 1996
- [j1]Yohji Watanabe, Ring Wong, Toshiaki Kirihata, Daisuke Kato, John K. DeBrosse, Takahiko Rara, Munehiro Yoshida, Rideo Mukai, Khandker N. Quader, Takeshi Nagai, Peter Poechmueller, Peter Pfefferl, Matthew R. Wordeman, Shuso Fujii:
A 286 mm2 256 Mb DRAM with ×32 both-ends DQ. IEEE J. Solid State Circuits 31(4): 567-574 (1996)
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last updated on 2024-04-25 05:43 CEST by the dblp team
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