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ORCIDBiman Chattopadhyay
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2010 – 2019
- 2018
[c8]Biman Chattopadhyay, Sharath N. Bhat, Gopalkrishna Nayak, Ravi Mehta:
A 12.5Gbps Transmitter for Multi-standard SERDES in 40nm Low Leakage CMOS Process. VLSID 2018: 13-18- 2016
- [c7]Jayesh Wadekar, Biman Chattopadhyay, Ravi Mehta, Gopalkrishna Nayak:
A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS. VLSID 2016: 236-239 - 2013
- [j1]Krishnaswamy Nagaraj, Anant S. Kamath, Karthik Subburaj, Biman Chattopadhyay, Gopalkrishna Nayak, Satyasai Evani, Neeraj P. Nayak, Indu Prathapan, Frank Zhang, Baher Haroun:
Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(3): 517-528 (2013) - 2012
- [c6]Ravi Mehta, Sumantra Seth, Siddharth Shashidharan, Biman Chattopadhyay, Sujoy Chakravarty:
A programmable, multi-GHz, wide-range duty cycle correction circuit in 45nm CMOS process. ESSCIRC 2012: 257-260 - [c5]Anant S. Kamath, Biman Chattopadhyay:
A wide output range, mismatch tolerant Sigma Delta DAC for digital PLL in 90nm CMOS. ISCAS 2012: 69-72 - 2011
- [c4]Biman Chattopadhyay, Anant S. Kamath, Satyasai Evani, Karthik Subburaj:
A 2GHz Digital PLL, with temperature lock range of -40°C to 125°C, in 45nm CMOS. CICC 2011: 1-4 - [c3]Biman Chattopadhyay, Anant S. Kamath, Gopalkrishna Nayak:
A 1.8GHz Digital PLL in 65nm CMOS. VLSI Design 2011: 47-51 - 2010
- [c2]Anant S. Kamath, Biman Chattopadhyay:
A 13MHz input, 480MHz output Fractional Phase Lock Loop with 1MHz bandwidth. ISCAS 2010: 501-504
2000 – 2009
- 2009
- [c1]Anant S. Kamath, Biman Chattopadhyay, Gopalkrishna Nayak:
A 65nm CMOS, ring-oscillator based, high accuracy Digital Phase Lock Loop for USB2.0. CICC 2009: 547-550
Coauthor Index
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