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ORCIDIEEE Design & Test of Computers, Volume 28
Volume 28, Number 1, January - February 2011
- Chris H. Kim, Leland Chang:
Guest editors' introduction: Nanoscale Memories Pose Unique Challenges. 6-8 - Kiyoo Itoh:
Embedded Memories: Progress and a Look into the Future. 10-13 - Darren Anand, Kevin W. Gorman, Mark Jacunski, Adrian Paparelli
:
Embedded DRAM in 45-nm Technology and Beyond. 14-21 - Fatih Hamzaoglu, Yih Wang, Pramod Kolar, Liqiong Wei, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang:
Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design. 22-31 - Masood Qazi, Mahmut E. Sinangil, Anantha P. Chandrakasan:
Challenges and Directions for Low-Voltage SRAM. 32-43 - Yuan Xie:
Modeling, Architecture, and Applications for Emerging Memory Technologies. 44-51 - Takayuki Kawahara:
Scalable Spin-Transfer Torque RAM Technology for Normally-Off Computing. 52-63 - Shyh-Shyuan Sheu, Kuo-Hsing Cheng, Meng-Fan Chang, Pei-Chia Chiang, Wen-Pin Lin, Heng-Yuan Lee, Pang-Shiu Chen, Yu-Sheng Chen, Frederick T. Chen, Ming-Jinn Tsai:
Fast-Write Resistive RAM (RRAM) for Embedded Applications. 64-71 - Andrew B. Kahng:
Design for manufacturability: Then and now. 76-77 - Igor L. Markov:
EDA: Synergy or sum of the parts? [review of "Electronic Design Automation: Synthesis, Verification and Test (Systems on Silicon" (Wang, L.-T., Eds., et al; 2009)]. 78-79
Volume 28, Number 2, March - April 2011
- Jason Cong, Glenn Reinman, Alex A. T. Bui, Vivek Sarkar:
Customizable Domain-Specific Computing. 6-15 - Luciano Ost, Guilherme Montez Guindani, Fernando Gehm Moraes, Leandro Soares Indrusiak, Sanna Määttä:
Exploring NoC-Based MPSoC Design Space with Power Estimation Models. 16-29 - Seung Eun Lee, Yoon Seok Yang, Gwan S. Choi, Wei Wu, Ravi R. Iyer:
Low-Power, Resilient Interconnection with Orthogonal Latin Squares. 30-39 - Chin-Lung Chuang, Chien-Nan Jimmy Liu:
Hybrid Testbench Acceleration for Reducing Communication Overhead. 40-51 - Mahmut Yilmaz, Mohammad Tehranipoor, Krishnendu Chakrabarty:
A Metric to Target Small-Delay Defects in Industrial Circuits. 52-61 - Katherine Shu-Min Li, Jr-Yang Huang:
Synthesizing Multiple Scan Trees to Optimize Test Application Time. 62-69 - Grant Martin:
Will hardware and software be codesigned? [review of "A Practical Introduction to Hardware/Software Codesign" (Schaumont, P.R.; 2010)]. 70-73 - Andrew B. Kahng:
Roads not taken. 74-75
Volume 28, Number 3, May - June 2011
- Prabhat Mishra, Zeljko Zilic, Sandeep K. Shukla:
Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models. 6-9 - Samar Abdi, Yonghyun Hwang, Lochi Yu, Gunar Schirner, Daniel D. Gajski:
Automatic TLM Generation for Early Validation of Multicore Systems. 10-19 - Weiwei Chen, Xu Han, Rainer Dömer:
Multicore Simulation of Transaction-Level Models Using the SoC Environment. 20-31 - Frédéric Pétrot, Nicolas Fournel, Patrice Gerin, Marius Gligor, Mian Muhammad Hamayun, Hao Shen:
On MPSoC Software Execution at the Transaction Level. 32-43 - Bart Vermeulen, Kees Goossens:
Interactive Debug of SoCs with Multiple Clocks. 44-51 - Zeljko Zilic, Prabhat Mishra, Sandeep K. Shukla:
Challenges of Rapidly Emerging Consumer Space Multiprocessors. 52-53 - Ilia Polian, John P. Hayes:
Selective Hardening: Toward Cost-Effective Error Tolerance. 54-63 - Nathan Kupp, He Huang, Yiorgos Makris, Petros Drineas:
Improving Analog and RF Device Yield through Performance Calibration. 64-75 - Stan Krolikoski:
Three Misconceptions Regarding Standards. 76-79 - Scott Davidson:
All About Liquid Scan Chains - and More [review of "Digital Microfluidic Biochips: Design Automation and Optimization" (Chakrabarty, K. and Xu, T.; 2010)]. 80-81 - Andrew B. Kahng:
The Future of Signoff. 86-89 - Sandeep K. Shukla, Prabhat Mishra, Zeljko Zilic:
A Brief History of Multiprocessors and EDA. 96
Volume 28, Number 4, July - August 2011
- George A. Constantinides, Nicola Nicolici:
Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research. 6-7 - George A. Constantinides, Adam B. Kinsman, Nicola Nicolici:
Numerical Data Representations for FPGA-Based Scientific Computing. 8-17 - Florent de Dinechin, Bogdan Pasca:
Designing Custom Arithmetic Data Paths with FloPoCo. 18-27 - Diego Sanchez-Roman, Gustavo Sutter, Sergio López-Buedo, Iván González, Francisco J. Gomez-Arribas, Javier Aracil, Francisco Palacios:
High-Level Languages and Floating-Point Arithmetic for FPGA-Based CFD Simulations. 28-37 - Joonseok Park, Pedro C. Diniz:
Data Reorganization and Prefetching of Pointer-Based Data Structures. 38-47 - Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch:
FPGA-Based Particle Recognition in the HADES Experiment. 48-57 - Devi Yalamarthy, Joel Coburn, Rajesh Gupta, Glen Edwards, Mark Kelly:
Computational Mass Spectrometry in a Reconfigurable Coherent Coprocessing Architecture. 58-67 - Greg Stitt, Alan D. George, Herman Lam, Melissa C. Smith, Vikas Aggarwal, Gongyu Wang, Casey Reardon, Brian Holland, Seth Koehler, James Coole:
An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing. 68-77 - Radu Marculescu, Paul Bogdan:
Cyberphysical Systems: Workload Modeling and Design Optimization. 78-87 - Shyue-Kung Lu, Yin Chen, Shi-Yu Huang, Cheng Wu:
Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores. 88-97 - Igor L. Markov:
Getting Your Bits in Order. 98-101 - Vaughn Betz:
FPGAs, Programming Models, and Kit Cars. 112
Volume 28, Number 5, September - October 2011
- Luciano Lavagno, Montek Singh:
Guest Editors' Introduction: Asynchronous Design Is Here to Stay (and Is More Mainstream Than You Thought). 4-6 - Steven M. Nowick, Montek Singh:
High-Performance Asynchronous Pipelines: An Overview. 8-22 - Ran Ginosar:
Metastability and Synchronizers: A Tutorial. 23-35 - Peter A. Beerel, Georgios D. Dimou, Andrew Lines:
Proteus: An ASIC Flow for GHz Asynchronous Designs. 36-51 - Jo C. Ebergen, Daniel F. Finchelstein, Russell Kao, Jon K. Lexau, David Hopkins:
An Evaluation of Asynchronous Stacks. 52-61 - Rafael Iankowski Soares, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Philippe Maurine, Lionel Torres:
A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines. 62-71 - Mariagrazia Graziano, Marco Vacca, Davide Blua, Maurizio Zamboni:
Asynchrony in Quantum-Dot Cellular Automata Nanocomputation: Elixir or Poison? 72-83 - Jean-Frédéric Christmann, Edith Beigné, Cyril Condemine, Pascal Vivet, Jérôme Willemin, Nicolas Leblond, Christian Piguet:
Bringing Robustness and Power Efficiency to Autonomous Energy-Harvesting Microsystems. 84-94 - Andrew B. Kahng:
Roadmapping Power. 104-106 - Stan Krolikoski:
Explicit and Implicit Contributions to Standards Groups. 107-109 - Nicolas Troquard:
Learning and Practice of the Property Specification Language. 110-111 - Al Davis:
Asynchronous FUD. 116
Volume 28, Number 6, November - December 2011
- Jiun-Lang Huang, Kwang-Ting (Tim) Cheng:
A Promising Alternative to Conventional Silicon. 6 - Tsung-Ching Huang, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng:
Robust Circuit Design for Flexible Electronics. 8-15 - William S. Wong, Tse Nga Ng, Sanjiv Sambandan, Michael Chabinyc:
Materials, Processing, and Testing of Flexible Image Sensor Arrays. 16-23 - Chester Liu, En-Hua Ma, Wen-En Wei, Chien-Mo James Li, I-Chun Cheng, Yung-Hui Yeh:
Placement Optimization of Flexible TFT Digital Circuits. 24-31 - Yindar Chuo, Badr Omrane, Clinton K. Landrock, Jeydmer Aristizabal, Donna Hohertz, Sasan Vosoogh-Grayli, Bozena Kaminska:
Powering the Future: Organic Solar Cells with Polymer Energy Storage. 32-40 - Peter C. Maxwell:
Adaptive Testing: Dealing with Process Variability. 41-49 - Youngsoo Shin, Seungwhun Paik:
Pulsed-Latch Circuits: A New Dimension in ASIC Design. 50-57 - Kirk A. Gray, Michael G. Pecht:
Long-Term Thermal Overstressing of Computers. 58-65 - Dallas Webster, Rick Hudgens, Donald Y. C. Lie:
Replacing Error Vector Magnitude Test with RF and Analog BISTs. 66-75 - Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Christophe Kelma:
RF Front-End Test Using Built-in Sensors. 76-84 - Bill Eklow:
Major Milestones for Two IEEE Standards Groups in 2011. 85-87 - Andrew B. Kahng:
Product Futures. 88-89
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