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2010 – 2019
- 2011
[j2]Darren Anand, Kevin W. Gorman, Mark Jacunski, Adrian Paparelli
:
Embedded DRAM in 45-nm Technology and Beyond. IEEE Des. Test Comput. 28(1): 14-21 (2011)- 2010
- [c2]Mark Jacunski, Darren Anand, Robert Busch, John A. Fifield, Matthew Lanahan, Paul Lane, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva:
A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns. CICC 2010: 1-4
2000 – 2009
- 2007
- [c1]Kevin W. Gorman, Michael Roberge, Adrian Paparelli, Gary Pomichter, Stephen Sliva, William Corbin:
Advancements in at-speed array BIST: multiple improvements. ITC 2007: 1-10 - 2005
- [j1]John E. Barth Jr., Darren Anand, Steve Burns, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Michael R. Nelms, Erik Nelson, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Stephen Sliva:
A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. IEEE J. Solid State Circuits 40(1): 213-222 (2005)
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