default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDITC 2012: Anaheim, CA, USA
- 2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-1594-4
- Masahiro Ishida, Kiyotaka Ichiyama, Daisuke Watanabe, Masayuki Kawabata, Toshiyuki Okayasu:
Real-time testing method for 16 Gbps 4-PAM signal interface. 1-10 - Ken Lanier:
Test/ATE vision 2020 - Entrepreneurship in test CEO panel. 1 - Xinli Gu:
Are industrial test problems real problems? I thought research has resolved them all! 1 - Eugene R. Atwood:
"Managing process variance in analog designs". 1 - Phil Nigh:
How are failure modes, defect types and test methods changing for 32nm/28nm technologies and beyond? 1-4 - Scott Davidson:
Testing high-frequency and low-power designs: Do the standard rules and tools apply? 1 - Zoe Conroy:
Are the IC guys helping or hindering board test? 1 - Nathan Kupp, Yiorgos Makris
:
Integrated optimization of semiconductor manufacturing: A machine learning approach. 1-10 - Dariusz Czysz, Janusz Rajski, Jerzy Tyszer:
Low power test application with selective compaction in VLSI designs. 1-10 - Friedrich Hapke, Michael Reese, Jason Rivers, A. Over, V. Ravikumar, Wilfried Redemund, Andreas Glowatz, Jürgen Schlöffel, Janusz Rajski:
Cell-aware Production test results from a 32-nm notebook processor. 1-9 - Teresa L. McLaurin, Frank Frederick, Rich Slobodnik:
The DFT challenges and solutions for the ARM® Cortex™-A15 Microprocessor. 1-9 - Mukesh Agrawal, Michael Richter, Krishnendu Chakrabarty:
A dynamic programming solution for optimizing test delivery in multicore SOCs. 1-10 - Weichi Ding, Mingde Pan, Wilson Wong, Daniel Chow, Mike Peng Li, Sergey Y. Shumarayev:
On-die instrumentation to solve challenges for 28nm, 28Gbps timing variability and stressing. 1-7 - Allan Ecker, Kenneth Blakkan, Mani Soma:
A digital method for phase noise measurement. 1-10 - Xian Wang, Hyun Woo Choi, Thomas Moon, Nicholas Tzou, Abhijit Chatterjee:
Higher than Nyquist test waveform synthesis and digital phase noise injection using time-interleaved mixed-mode data converters. 1-10 - Xiao Liu, Qiang Xu:
On efficient silicon debug with flexible trace interconnection fabric. 1-9 - Ming Gao, Peter Lisherness, Kwang-Ting (Tim) Cheng:
Adaptive test selection for post-silicon timing validation: A data mining approach. 1-7 - Adam B. Kinsman, Ho Fai Ko, Nicola Nicolici:
In-system constrained-random stimuli generation for post-silicon validation. 1-10 - Jose Moreira, Marc Moessinger, Koji Sasaki, Takayuki Nakamura:
Driver sharing challenges for DDR4 high-volume testing with ATE. 1-10 - Shoji Kojima, Yasuyuki Arai, Tasuku Fujibe, Tsuyoshi Ataka, Atsushi Ono, Ken-ichi Sawada, Daisuke Watanabe:
8Gbps CMOS pin electronics hardware macro with simultaneous bi-directional capability. 1-9 - David C. Keezer, Te-Hui Chen, Carl Edward Gray, Hyun Woo Choi, Sungyeol Kim, Seongkwan Lee, Hosun Yoo:
Multi-gigahertz arbitrary timing generator and data pattern serializer/formatter. 1-11 - Nathan Kupp, Ke Huang, John M. Carulli Jr., Yiorgos Makris:
Spatial estimation of wafer measurement parameters using Gaussian process models. 1-8 - B. Seshadri, P. Gupta, Y. T. Lin, Bruce Cory:
Systematic defect screening in controlled experiments using volume diagnosis. 1-7 - Nik Sumikawa, Jeff Tikkanen, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir:
Screening customer returns with multivariate test analysis. 1-10 - Xiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang:
On pinpoint capture power management in at-speed scan test generation. 1-10 - Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue:
A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation. 1-8 - Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker:
Functional test of small-delay faults using SAT and Craig interpolation. 1-8 - Takahiro Nakajima, Takeshi Yaguchi, Hajime Sugimura:
An ATE architecture for implementing very high efficiency concurrent testing. 1-10 - Nicholas Tzou, Debesh Bhatta, Sen-Wen Hsiao, Hyun Woo Choi, Abhijit Chatterjee:
Low-cost wideband periodic signal reconstruction using incoherent undersampling and back-end cost optimization. 1-10 - Masahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada:
Power integrity control of ATE for emulating power supply fluctuations on customer environment. 1-10 - Jong Chul Lee, Faycel Kouteib, Roman Lysecky:
Event-driven framework for configurable runtime system observability for SOC designs. 1-10 - Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich:
Modeling, verification and pattern generation for reconfigurable scan networks. 1-9 - Min Li, Kelson Gent, Michael S. Hsiao:
Design validation of RTL circuits using evolutionary swarm intelligence. 1-8 - Sreenivaas S. Muthyala, Nur A. Touba:
Improving test compression by retaining non-pivot free variables in sequential linear decompressors. 1-7 - Peter Wohl, John A. Waicukauski, Frederic Neuveux, Jonathon E. Colburn:
Hybrid selector for high-X scan compression. 1-10 - Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski:
Low power programmable PRPG with enhanced fault coverage gradient. 1-9 - Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Olivier Potin, Michel Renovell:
Making predictive analog/RF alternate test strategy independent of training set size. 1-9 - Zhongjun Yu, Degang Chen:
Algorithm for dramatically improved efficiency in ADC linearity test. 1-10 - Gerald Hilber, Dominik Gruber, Michael Sams, Timm Ostermann:
Calibration of a flexible high precision Power-On Reset during production test. 1-7 - Franco Stellari, Thomas Cowell, Peilin Song, Michael Sorna, Zeynep Toprak Deniz, John F. Bulzacchelli, Nandita A. Mitra:
Root cause identification of an hard-to-find on-chip power supply coupling fail. 1-7 - Xiaoxin Fan, Huaxing Tang, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Brady Benware:
Improved volume diagnosis throughput using dynamic design partitioning. 1-10 - Yuxi Liu, Qiang Xu:
On modeling faults in FinFET logic circuits. 1-9 - Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter:
A unified method for parametric fault characterization of post-bond TSVs. 1-10 - Eshan Singh:
Impact of Radial defect clustering on 3D stacked IC yield from wafer to wafer stacking. 1-7 - Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty, Sung Kyu Lim:
Scan test of die logic in 3D ICs using TSV probing. 1-8 - Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen:
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. 1-10 - Kenneth P. Parker:
Capacitive sensing testability in complex memory devices. 1-6 - Igor Aleksejev, Artur Jutman, Sergei Devadze, Sergei Odintsov, Thomas Wenzel:
FPGA-based synthetic instrumentation for board test. 1-10 - Zoe Conroy, James J. Grealish, Harrison Miles, Anthony J. Suto, Alfred L. Crouch, Skip Meyers:
Board assisted-BIST: Long and short term solutions for testpoint erosion - Reaching into the DFx toolbox. 1-10 - Michele Portolan:
Packet-based JTAG for remote testing. 1-6 - Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, Ching-Nen Peng, Min-Jer Wang:
A memory yield improvement scheme combining built-in self-repair and error correction codes. 1-9 - Hao-Yu Yang, Chen-Wei Lin, Hung-Hsin Chen, Mango Chia-Tso Chao, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang:
Testing strategies for a 9T sub-threshold SRAM. 1-10 - Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Low-power SRAMs power mode control logic: Failure analysis and test solutions. 1-10 - Yun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A built-in self-test scheme for 3D RAMs. 1-9 - Matthew Beckler, R. D. (Shawn) Blanton:
On-chip diagnosis for early-life and wear-out failures. 1-10 - Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura:
DART: Dependable VLSI test architecture and its implementation. 1-10 - Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta:
A design flow to maximize yield/area of physical devices via redundancy. 1-10 - Somayeh Sadeghi Kohan, Majid Namaki-Shoushtari, Fatemeh Javaheri, Zainalabedin Navabi:
BS 1149.1 extensions for an online interconnect fault detection and recovery. 1-9 - Shahrzad Mirkhani, Jacob A. Abraham, Toai Vo, Hong Shin Jun, Bill Eklow:
FALCON: Rapid statistical fault coverage estimation for complex designs. 1-10 - Animesh Khare, P. Kishore, S. Reddy, K. Rajan, A. Sanghani:
Methodology for fault grading high speed I/O interfaces used in complex Graphics Processing Unit. 1-8 - Vinayak Kamath, Wen Chen, Nik Sumikawa, Li-C. Wang:
Functional test content optimization for peak-power validation - An experimental study. 1-10 - Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Christophe Kelma:
Experiences with non-intrusive sensors for RF built-in test. 1-8 - Matthieu Dubois, Emeric de Foucauld, Christopher Mounet, Serigne Dia, Cedric Mayor:
A frequency measurement BIST implementation targeting gigahertz application. 1-8 - Josep Altet, Diego Mateo, Didac Gómez, Xavier Perpiñà, Miquel Vellvehí, Xavier Jordà:
DC temperature measurements for power gain monitoring in RF power amplifiers. 1-8 - Motoo Ueda, Shinichi Ishikawa, Masaru Goishi, Satoru Kitagawa, Hiroshi Araki, Shuichi Inage:
Automated system level functional test program generation on ATE from EDA using Functional Test Abstraction. 1-7 - Thomas Moon, Hyun Woo Choi, Abhijit Chatterjee:
Low cost high-speed test data acquisition: Accurate period estimation driven signal reconstruction using incoherent subsampling. 1-9 - Takashi Ito, Hideo Okawara, Jinlei Liu:
RNA: Advanced phase tracking method for digital waveform reconstruction. 1-9 - Xiaoxiao Wang, Dat Tran, Saji George, LeRoy Winemberg, Nisar Ahmed, Steve Palosh, Allan Dobin, Mohammad Tehranipoor:
Radic: A standard-cell-based sensor for on-chip aging and flip-flop metastability measurements. 1-9 - Michail Maniatakos, Maria K. Michael, Yiorgos Makris:
Vulnerability-based Interleaving for Multi-Bit Upset (MBU) protection in modern microprocessors. 1-8 - Nik Sumikawa, Li-C. Wang, Magdy S. Abadir:
An experiment of burn-in time reduction based on parametric test analysis. 1-10
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-09-13 00:29 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
