Hardware/Software Co-design
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September, 2001
“Traditional” Design Flow
Informal Specification,
Requirements
Software Hardware
model model
Simulation
Testin
Scheduling, Hardware
Software
g
Generation Synthesis
Software Communication Hardware
blocks Synthesis blocks
Prototyping
Product Fabrication
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Codesign
September, 2001
Petru Eles
Hw/Sw Co-Design Flow
System
Simulation
specification
Hardw/Softw
Partitioning
Partitioned
model
System Level
Scheduling
Part. model, Hardw./
Softw.
Cosimulation
Schedule
Communication
Synthesis
Software Hardw./ Hardware
model Softw. model
Cosimulation
Software Hardware
Generation
Lower Levels
Synthesis
Software Hardw./ Hardware
blocks Softw. blocks
Cosimulation
Emulation,
Prototyping
Product Fabrication
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Codesign
September, 2001
Petru Eles
Some Issues
■ Distributed Systems & System on chip
■ Processor design & Reconfigurable systems
■ Compiling (software synthesis)
■ Low power
■ IP-based design (reuse)
■ System specification
■ Formal methods
■ Verification and testing
■ Real-time Systems
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Petru Eles September, 2001
Distributed Real-Time Systems
Classical real-time research
■ Covers only a limited part of the design flow
■ Assumptions are often unrealistic
❚ Task models are too simple
❚ The underlying architecture is assumed fixed and is not considered
as part of the global design/optimization problem;
The same for the communication infrastructure.
❚ Emphasis on the “worst case”.
❚ --------------
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Petru Eles September, 2001
System on Chip
❚ Analog and digital on the same chip
❚ Problems related to
Processor Cache DMA Memory
interconnections are becoming
❚ dominant.
Timing closure.
In t erconnection
Net w ork
❚ Bus-based architectures will be
Recon- replaced by “networks on
AD/DA fig urabl e Peripheral
logic ❚ chip”.
Customized cashes and memories.
❚ Testability!
❚ ----------------
-
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Petru Eles September, 2001
Processor Design
Partitioning across the horizontal line, as opposed to ...... see next slide
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---------
---------
---------
---------
---------
---------
--------- Software
---------
--------- Profiling,
Instruction set
Analysis Hardware
(ASIP)
---------
---------
--------- A main issue:
---------
--------- compilers and programming environments!
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Petru Eles September, 2001
Processor Design (cont’d)
Partitioning across the vertical line
---------------
---------------
---------------
---------------
---------------
---------------
---------------
---------------
Partitionin
&mappin
g
g
Soft w are Soft w are Soft w are Hard w Hard w
(Processor) (Processor) (Processor) are are
(ASIC) (ASIC)
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Petru Eles September, 2001
Parameterized Platforms
Application
development
(on ref. chip)
Detailed
Processor Cache DMA Memo ry Bridge str uc t ural
model
System bus Parameter
optimization
Peripheral bus (sim. &
estim.)
Recon-
Peripheral Ne w
fig urabl e
System
logic generation
P roduct
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Petru Eles September, 2001
Software Synthesis
What makes software synthesis for embedded systems different?
■ The need of highly optimized code in order to make use of
the particular features of the underlying architecture.
■ Large compilation times can be tolerated.
■ Time constraints have to be considered during
compilation.
■ Scheduling aspects:
❚ at instruction level;
❚ at task level.
■ The need of performant easy-to-use retargetable
compilers.
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Petru Eles September, 2001
Software Synthesis (cont’d)
What makes it a Hardware/Software problem?
■ The hardware support has to be considered during software generation.
■ Efficient retargetable compilers are important tools for concurrent
development of software and of the underlying hardware
(for example ASIPs).
■ Hardware Specification is an important aspect of retargetable
compiling.
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Petru Eles September, 2001
Low Power
consume
energy
❚ Trade-offs: flexibility, power,
performance, time to market.
d
GP proc.
high
❚ There is an obvious trend
magnitud
order of
ASIP towards software
❚ implementation.
Because of power/performance,
e
med.
FPGA part of the functionality is imple-
magnitud
order of
mented with ASIC/FPGA/ASIP.
This makes the difference!
low ASIC
e
low med. high flexibility
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Petru Eles September, 2001
Low Power (cont’d)
■ Power optimization at circuit and gate level Power
■ optimization at system level
❚ Dynamic power management
- shutdown of idle resources
- variable supply voltage
❚ Mapping and scheduling with power optimization
❚ Code generation for low power
❚ Customized cache memory (to reduce memory access and bus
traffic)
❚ Information encoding
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Petru Eles September, 2001
Specification/Modeling/
Verification
Embedded systems are inherently heterogeneous
discrete
Specification imperative FSMs dataflow event
partitioning
Refinement
compiling softw. synth HLS LS
Lower level SW SW
processor processor ASIC glue logic
of abstraction model model
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Petru Eles September, 2001
Specification/Modeling/Verification (cont’d)
■ A formal model (possibly more) has to be part of a design methodology.
■ Allows unambiguous specification and analysis of the design.
■ The effect of transformations on the design is well-defined.
■ It is possible to formally reason about correctness.
Complexity!
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Petru Eles September, 2001
Specification Languages
■ A single specification language can be used for the whole system; does
not necessarily mean that we have a homogeneous specification:
■ Several languages can be used for system specification
❚ specific languages for the hardware and software part;
❚ different languages can be used, depending on the selected model
of computation or because of other reasons.
❚ How to perform (co)simulation?
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Petru Eles September, 2001
Specification Languages (cont’d)
■ General purpose languages (Ada, C, C++, SystemC, Java, UML, Matlab)
■ Hardware description languages (VHDL, Verilog)
■ Synchronous languages (FSM based): Esterel, Lustre, Signal,
StateCharts.
■ Networks of communicating processes: CSP, Lotos, SDL.
■ Data-flow languages: Silage
■ Functional programming languages: Haskell, SML.
■ Algebraic notations: VDM, Z, B.
■ Will we get the System Specification Language?
■ Will multi-language specification become (remain) the standard?
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Petru Eles September, 2001
Verification and Testing
System
specificatio n
Ref_step 1
System-level synthesis
model 1
(looks for errors in specification&design)
D E S I G N VALI DAT I O N
formal verification & simulation
Ref_step 2
model 2
Ref_step n
model_h model_s
system
synthesis
architecture
Soft w are synthesis
Ref_step_h 1 Ref_step_s 1
model_h 1 model_s 1
Hard w
Ref_step_h m Ref_step_s k
are
model_h m model_s k
Fabrication
PRODUCT TESTING
looks for: design errors
PRODUCT fabrication defects
physical failures
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Codesign
September, 2001
Petru Eles
Final Remarks
■ The real issue here is design of embedded systems
❚ Start from the specification at high abstraction level
❚ Consider complex trade-offs
❚ Concentrate on early design steps
❚ Hardware architecture and software are jointly
developed
❚ Keep a global view and master heterogeneity
■ Important progress has been achieved on certain particular aspects.
■ Some progress towards a methodology and supporting tools.
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Petru Eles September, 2001
■ Software Performance Estimation by Static Analysis
❚ Program path analysis
❚ Microarchitecture modeling
- Cache memory
- Pipeline architecture
- Branch prediction
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Codesign Petru Eles September, 2001
■ System-Level Power/Energy Optimization
❚ Main issues in system-level power/energy
optimization
- System modeling
- Hardware and software implementation
- Dynamic power management
- Computing, memory, communication
❚ Dynamic power management
-Modeling issues
-Predictive, adaptive, and stochastic techniques
❚ Power estimation and low power software
generation
❚ Low power/energy scheduling for real-time
systems
- Variable voltage systems
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Static and dynamic approaches 48 of 52
Codesign Petru Eles September, 2001
- Energy efficient priority-based scheduling
■ Hardware/Software Codesign Environments
❚ The Cosyma System
❚ The Cosmos Environment
❚ The SpecSyn Environment
❚ Synthesis of Distributed Embedded
Systems
❚ The POLIS Environment
❚ The CoWare Environment
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