Noida Institute of Engineering and Technology, GR.

Noida
(An Autonomous Institute)
School of Computer Science & Engineering in Emerging
Technologies

Introduction

Unit: 1

Logic Design & Computer

Swarnima
Architecture (ACSAI0302)
Assistant Professor
B Tech (AIML)- 3rd Sem NIET, Greater Noida

Swarnima Logic Design & Computer Architecture Unit 1

1
08/09/2025
 Evaluation scheme

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 2
 Subject Syllabus
Course Contents / Syllabus
UNIT-I Introduction 8 Hours
Basics of Logic Design: Basic of number System, Boolean algebra, Half Adder and Full
Adder, Half Subtractor and Full Subtractor, Multiplexer, Encoder, Decoder
Computer Organization and Architecture, Functional units of digital system and their
interconnections, buses, bus architecture, types of buses and bus arbitration and it’s
types. Register, bus and memory transfer. Process or organization, general registers
organization, stack organization and addressing modes.

UNIT-II ALU Unit 8 Hours

Arithmetic and logic unit: Lookahead carries adders. Multiplication: Signed operand
multiplication, Booth’s algorithm and array multiplier. Division and logic operations.
Floating point arithmetic operation, Arithmetic & logic unit design. IEEE Standard for
Floating Point Numbers.
UNIT-III Control Unit 8 hours
Control Unit: Instruction types, formats, instruction cycles and sub cycles (fetch and
execute etc.), microoperations, execution of a complete instruction. Program Control,
Reduced Instruction Set Computer, Complex Instruction Set Computer, Pipelining.
Hardwire and microprogrammed control, Concept of horizontal and vertical
microprogramming, Flynn's classification.
Swarnima ogic Design & Computer Architecture Unit 1
08/09/2025 3
 Subject Syllabus
Course Contents / Syllabus

UNIT-IV Memory Unit 8 hours

Memory: Basic concept and hierarchy, semiconductor RAM memories, 2D & 2 1/2D
memory organization. ROM memories. Cache memories: concept and design issues &
performance, address mapping and replacement Auxiliary memories: magnetic disk,
magnetic tape and optical disks Virtual memory: concept implementation, Memory
Latency, Memory Bandwidth, Memory Seek Time.

UNIT-V Input/Output 8 hours

Peripheral devices, I/O interface, I/O ports, Interrupts: interrupt hardware, types of
interrupts and exceptions. Modes of Data Transfer: Programmed I/O, interrupt initiated
I/O and Direct Memory Access. ,I/O channels and processors. Serial Communication:
Synchronous & asynchronous communication.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 4
 Branch wise Applications
Computer Science:

Understanding of Computer Organization and Architecture is required

for:
• Performance analysis of practical software
• Parallel Software and its execution
• High performance databases
• Modern Compilers and Code optimization
• High performance game programming

Other applications

• Bio-informatics, Data science using python, Web programming

For high performance computing, we require COA background.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 5
 Course Objective

• Discuss the basic concepts and structure of computers.

• Understand concepts of register transfer logic and arithmetic
operations.
• Explain different types of addressing modes and memory
organization.
• Understand the concepts of memory system and Learn the different
types of memories to store data.
• Explain the various types of interrupts and modes of data transfer.

• NEW----To understand the types of

organizations, structures, and functions of
computers, design of arithmetic and logic units,
and float point arithmetic. To understand the
concepts of the memory system,
communication with I/O devices, and
interfaces.
Swarnima Logic Design & Computer Architecture Unit 1
08/09/2025 6
 Course Outcomes

Course outcomes : After completion of this course students will be able to

CO 1 Understand the basic structure and operation of a digital K2

computer system
CO 2 Analyze the design of arithmetic & logic unit and understand the K4
fixed point and floating-point arithmetic operations.
CO 3 Implement control unit techniques and the concept of Pipelining K3

CO 4 Understand the hierarchical memory system, cache memories K2

and virtual memory.
CO 5 Understand different ways of communicating with I/O devices K2
and standard I/O interfaces.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 7
 Program Outcomes
• Program Outcomes are narrow statements that describe what the students
are expected to know and would be able to do upon the graduation.

• These relate to the skills, knowledge, and behavior that students acquire
through the programmed.

1. Engineering knowledge
2. Problem analysis 9. Individual and team work
3. Design/development of solutions 10. Communication
4. Conduct investigations of complex 11. Project management and
problems finance
5. Modern tool usage 12. Life-long learning
6. The engineer and society
7. Environment and sustainability
8. Ethics

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 8
 CO-PO Mapping

Logic Design & Computer Architecture

(ACSAI0302)

PO PO PO
CO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 10 11 12
CO1 3 2 1 1 1 1 1 - 1 1 1 2
CO2 2 2 2 2 1 1 - 1 1 1 1 2
CO3 3 2 2 1 2 2 1 1 2 2 1 2
CO4 3 2 2 2 2 1 1 - 1 1 1 2
CO5 2 2 2 1 2 - 1 - 1 2 2 2

Average 2.6 2 1.8 1.4 1.6 1 0.8 0.4 1.2 1.4 1.2 2

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 9
 Program Educational Objectives

PEO1: Solve real-time complex problems and adapt to technological

changes with the ability of lifelong learning.
PEO2: Work as data scientists, entrepreneurs, and bureaucrats for
the goodwill of the society and pursue higher education.
PEO3: Exhibit professional ethics and moral values with good
leadership qualities and effective interpersonal skills.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 10
 Result Analysis

Department Result Individual Result

Computer 100%
Organization
and Architecture

Renewable 98.57%
Energy
Resources

Universal 90.74%
Human Values

Introduction to 95.61%
Microprocessor

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 11
 End Semester Question Paper Template

Question Paper
Template -100 Marks

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 12
 Prerequisite and Recap

• Basic knowledge of computer systems.

• Logic gates and their operations.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 13
 Brief Introduction about Subject

The Computer Organization and architecture is one of the most

important and comprehensive subject that includes many foundational
concepts and knowledge used in design of a computer system. This
subject provides in-depth knowledge of internal working, structuring,
and implementation of a computer system.

The COA important topics include all the fundamental concepts such
as computer system functional units , processor micro architecture ,
program instructions, instruction formats , addressing modes ,
instruction pipelining, memory organization , instruction cycle,
interrupts and other important related topics.

Video link: [Link]

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 14
 Unit Content

Basics of Logic Design: Basic of number System, Boolean algebra, Half

Adder and Full Adder, Half Subtractor and Full Subtractor, Multiplexer,
Encoder, Decoder
Computer Organization and Architecture, Functional units of digital
system and their interconnections, buses, bus architecture, types of
buses and bus arbitration and it’s types. Register, bus and memory
transfer. Process or organization, general registers organization, stack
organization and addressing modes.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 15
 Unit Objective

• To understand the basic concepts and structure of

computers.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 16
 Introduction to Topic 1

Name of Topic Objective of Topic Mapping with CO

Students will be able
Basics of Number to understand CO 1
System

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 17

 Basics of Number System
• In digital electronics, the number system is used for representing the
information.
• The number system has different bases and the most common of them
are the decimal, binary, octal, and hexadecimal.
• The base or radix of the number system is the total number of the digit
used in the number system.
• Suppose if the number system representing the digit from 0 – 9 then
the base of the system is the 10.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 18
 Basics of Number System
Binary to Decimal conversion
 Take each digit in the binary number and multiply it with its place
value.
 The sum of all the above products will give the equivalent
decimal number.

• Ex :- (1011)2 to decimal number.

• Sol :- (1011)2 = (1 x 23) + ( 0 x 22) + (1 x 21) + (1 x 20 )

= (1 x 8) + ( 0 x 4) + (1 x 2) + (1 x 1)
= (11)10

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 19
 Basics of Number System
• Binary to Octal number system

• Ex :- Convert the binary number (1110101)2 into octal number.

• (1110101)2 = 001 110 101

• = (165)8

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 20
 Basics of Number System
• Binary to Hexadecimal number system

• Ex :- Convert the binary number (1010101010)2 in to

hexadecimal number.
• (1010101010)2 = 0010 1010 1010

• = (2AA)16

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 21
 Basics of Number System
• Decimal to Binary conversion
• The decimal number is converted in to binary number by using successive
divisions method.
1. The decimal number (i.e. dividend) is divided by 2 (i.e. divisor).
2. If ‘1’ or “0” occurs as remainder, transfer that ‘1’ or “0” to the binary record.
3. Now take quotient as dividend and divide it by 2 and transfer the remainder to
the binary record.
4. The same procedure is continued until the quotient becomes zero
5. The last remainder is taken as most significant bit (MSB).
6. The first remainder is taken as least significant bit (LSB).
7. The equivalent binary number comprises with all the remainders in successive
divisions method in the order from MSB (bottom) to LSB (top).

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 22
 Basics of Number System

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 23
 Basics of Number System
• Hexadecimal to Decimal Conversion

• Ex: (5C7)16 to decimal

• Sol:- (5C7)16 = (5x162) + (C x161) + (7 x160)
• = 1280 + 192 + 7
• = (1479)10

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 24
 Basics of Number System
• Decimal to Hexadecimal Conversion

• Ex :- Convert the decimal number (415)10 in to hexadecimal

number.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 25
 Introduction to Topic 1

Name of Topic Objective of Topic Mapping with CO

Students will be able
Functional units of to understand about CO 1
digital system and different units of
their interconnections computer and how
they are connected

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 26

 Introduction

• Computer Organization and Architecture provides in-depth knowledge

of internal working, structuring, and implementation of a computer
system
Computer Architecture
• It is concerned with the way hardware components are connected
together to form a computer system.

Computer Organization
• It is concerned with the structure and behaviour of a computer system
as seen by the user.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 27
 Introduction

• Computer Organization and Architecture provides in-depth knowledge

of internal working, structuring, and implementation of a computer
system
Computer Architecture
• It is concerned with the way hardware components are connected
together to form a computer system.

Computer Organization
• It is concerned with the structure and behaviour of a computer system
as seen by the user.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 28
 Introduction

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 29
 Introduction

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 30
 Introduction

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 31
 Introduction

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 32
 Introduction

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 33
 Introduction

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 34
 Functional Units of Computer System

Block Diagram

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 35
 Functional Units of Computer System
1. Input Unit :
• The input unit consists of input devices that are attached to the
computer.
• These devices take input and convert it into binary language that the
computer understands.
• Common input devices are keyboard, mouse, joystick, scanner etc.

2. Central Processing Unit (CPU) :

• The CPU is called the brain of the computer because it is the control
centre of the computer.
• It first fetches instructions from memory and then interprets them so
as to know what is to be done.
• CPU executes or performs the required computation and then either
stores the output or displays on the output device
Swarnima Logic Design & Computer Architecture Unit 1
08/09/2025 36
 Functional Units of Computer System
3. Arithmetic and Logic Unit (ALU) :
• It performs mathematical calculations and takes logical decisions.
• Arithmetic calculations include addition, subtraction, multiplication
and division.
• Logical decisions involve comparison of two data items to see which
one is larger or smaller or equal.

4. Control Unit :
• It coordinates and controls the data flow in and out of CPU and also
controls all the operations of ALU, memory registers and
input/output units.
• It decodes the fetched instruction, interprets it and sends control
signals to input/output devices until the required operation is done
properly by ALU and memory.
Swarnima Logic Design & Computer Architecture Unit 1
08/09/2025 37
 Functional Units of Computer System

5. Memory :
• Memory attached to the CPU is used for storage of data and
instructions and is called internal memory.
• The internal memory is divided into many storage locations, each of
which can store data or instructions

6. Output Unit :
• The output unit consists of output devices that are attached with
the computer.
• It converts the binary data coming from CPU to human
understandable form.
• The common output devices are monitor, printer, plotter etc.

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 38

 Interconnection of Functional unit

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 39
 Memory
1. Primary / Main memory:
• The memory unit that establishes direct communication with the CPU
is called Main Memory. The main memory is often referred to as RAM
(Random Access Memory).
• It holds the data and instructions that the processor is currently
working on.
2. Secondary Memory / Mass Storage:
• The contents of the secondary memory first get transferred to the
primary memory and then are accessed by the processor, this is
because the processor does not directly interact with the secondary
memory.
• The memory units that provide backup storage are called Auxiliary
Memory. For instance, magnetic disks and magnetic tapes are the most
commonly used auxiliary memories.

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 40

 Daily Quiz
1. ______ is considered as the brain of the computer.
2. ________ is smallest unit of the information.
3. _________ is the decimal equivalent of the binary number 10111.
4. _______ section is used to perform logic operations such as comparing,
selecting, matching of data.
5. ________ unit is used to store data and instructions.
6. The functions of sequencing and execution are performed by using
a) Input Signals
b) Output Signals
c) Control Signals
d) CPU
7. ________ is a way in which the hardware components of a computer
are connected to each other.
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 41
 Daily Quiz with Answers
1. ______ is considered as the brain of the computer. ( CPU )
2. ________ is smallest unit of the information? (Bit)
3. _________ is the decimal equivalent of the binary number 10111? (23)
4. _______ section is to perform logic operations such as comparing,
selecting, matching, and merging of data? (ALU/Logic section )
5. _________ is used to store data and instructions. (Memory)
6. The functions of sequencing and execution are performed by using
a) Input Signals
b) Output Signals
c) Control Signals
d) CPU
7. ________ is a way in which the hardware components of a computer are
connected to eachSwarnima
08/09/2025
other. (Computer Architecture) Unit 1
Logic Design & Computer Architecture 42
 Recap
• Computer Organization and Architecture provides in-depth knowledge
of internal working, structuring, and implementation of a computer
system.
• Computer Architecture is concerned with the way hardware components
are connected together to form a computer system.
• Computer Organization is concerned with the structure and behaviour of
a computer system as seen by the user.
• Computer consists of different blocks such as Input, output, Control unit,
memory unit and ALU.

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 43

 Introduction to Topic 2

Name of Topic Objective of Topic Mapping with CO

Students will be able
Buses, bus to know the CO 1
architecture, Types of architecture and
buses types of buses.

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 44

 BUS

BUS
• A bus is a common pathway through which information flows from
one computer component to another.
• It is a subsystem that is used to transfer data and other information
between devices.
• Means various devices in computer like(Memory, CPU, I/O and
Other) are communicate with each other through buses.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 45
 Bus Architecture

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 46
 System Bus

• A system bus is a single computer bus that connects the major

components of a computer system, combining the functions of
a data bus to carry information, an address bus to determine where
it should be sent or read from, and a control bus to determine its
operation.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 47
 System Bus

• Types of Computer BUS:

1. Data Bus
2. Address Bus
3. Control Bus

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 48
 System Bus
1. Data bus
• It is a bidirectional pathway that carries the actual data (information)
to and from the main memory.
• Data Lines provide a path for moving data between system modules.
• It is bidirectional which means data lines are used to transfer data in
both directions.
• CPU can read data on these lines from memory as well as send data
out of these lines to a memory location or to a port.
• The no. of lines in data lines are either 8,16,32 or more depending on
architecture.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 49
 System Bus

2. Address bus
• Address Lines are collectively called as address bus.
• It is a unidirectional pathway that allows information to travel in
only one direction.
• No. of lines in address are usually 16,20,24, or more depending on
type and architecture of bus
• It is an internal channel from CPU to Memory across which the
address of data(not data) are transmitted.
• It is used to identify the source or destination of data.
• Here the communication is one way that is, the address is send
from CPU to Memory and I/O Port but not Memory and I/O port
send address to CPU on that line and hence these lines are
unidirectional.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 50
 System Bus

3. Control bus
• It carries the control and timing signals needed to coordinate the
activities of the entire computer.
• They are used by CPUs for Communicating with other devices
within the computer.
• They are bidirectional.
• Typical Control Lines signals are
Memory Read
Memory Write
I/O Read
I/O Write ,etc

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 51
 Bus Structure

1. Single Bus Structure –

All units are connected to the same bus.

2. Multiple Bus Structure

a) Traditional Configuration
Uses three buses – local bus, system bus and expanded bus.

b) High Speed BUS Configuration

Uses high speed bus along with three buses – local bus, system bus and
expanded bus used in traditional configuration.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 52
 Single Bus Structure

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 53
 Traditional Bus Configuration

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 54
 Traditional Bus Configuration
• The traditional bus connection uses three buses local bus , system
bus and expansion bus
1. Local bus connects the processor to cache memory and may
support one or more local devices.
2. The cache memory controller connects the cache to local bus and
to the system bus.
3. System bus also connects main memory module.
4. Input /output transfer to and from the main memory across the
system bus do not interface with the processor activity because
process accesses cache memory.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 55
 Traditional Bus Configuration
• An expansion bus interface buffers data transfers between the bus
and the I/O controllers on the expansion bus.
• Some typical I/O devices that might be attached to the expansion
bus include
Network cards (LAN)
SCSI (Small Computer System Interface)
Modem
Serial Com

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 56
 Traditional Bus Configuration
Advantages of Traditional Bus Architecture
• A separate cache structure insulates the processor from the
requirement to access the main memory frequently.
This arrangement allows the system to support a wide variety of I/O
devices and, at the same time, insulate memory to processor traffic
from I/O traffic.
Disadvantages of Traditional Bus Architecture
• The traditional bus architecture is reasonably efficient but begins to
break down as higher, and higher performance is seen in the I/O
devices.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 57
 High Speed Bus Configuration

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 58
 High Speed Bus Configuration
• There is a local bus that connects the processor to a cache controller, which
is, in turn, connected to a system bus that supports the main memory.
• The cache controller is integrated into a bridge or buffering device that
connects to a high-speed bus.
• This (High Speed) bus supports connections to high-speed LANs, such as
Fast Ethernet at 100 Mbps, video and graphics workstation controllers to
local peripheral busses, including SCSI and Firewire.
• An expansion bus still supports lower-speed devices, with an interface
buffering traffic between the expansion bus and the high-speed bus.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 59
 High Speed Bus Configuration
Advantages of High-Performance Bus Architecture
• The advantage of this arrangement is that the high-speed bus brings high-
demand devices into closer integration with the processor and, at the same
time, is independent of the processor.
So changes in processor architecture also do not affect the high-speed bus.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 60
 Daily Quiz

1. ________ bus carries information between processors and

peripherals.
2. _______ are unidirectional bus.
3. _________ bus controls the sequencing of read/write operations.
4. _____ is a common pathway through which information flows
from one computer component to another.
5. Control bus is Unidirectional. T/F

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 61

 Daily Quiz

1. ________ bus carries information between processors and peripherals.

(Data Bus)
2. _______ are unidirectional bus. (Address Bus)
3. _________ bus controls the sequencing of read/write operations.
(Control Bus)
4. _____ is a common pathway through which information flows from one
computer component to another. (Bus)
5. Control bus is Unidirectional. False

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 62

 Recap

Bus Type Description

Address bus A unidirectional pathway – information can only flow

one way
A bi-directional pathway – information can flow in two
Data bus directions

Control bus Carries the control and timing signals needed to

coordinate the activities of the entire computer

08/09/2025 63
Swarnima Logic Design & Computer Architecture Unit 1
 Introduction to Topic 3

Name of Topic Objective of Topic Mapping with CO

Students will be able
• Bus arbitration to know the different CO 1
schemes of bus
arbitration

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 64

 Bus Arbitration
Bus Arbitration
It refers to the process by which the current bus master accesses and
then leaves the control of the bus and passes it to the another bus
requesting processor unit.

• Bus master :The controller that has access to a bus at an instance.

• Bus Arbiter: It decides who would become current bus master.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 65
 Bus Arbitration
There are two approaches to bus arbitration:
1. Centralized bus arbitration
A single bus arbiter performs the required arbitration and it can be
either a processor or a separate DMA controller.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 66
 Bus Arbitration

2. Distributed bus arbitration

All devices participate in the selection of the next bus master.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 67
 Bus Arbitration

Methods of BUS Arbitration

There are three arbitration schemes which run on centralized arbitration.

1. Daisy Chaining method

2. Polling method

3. Independent Request method

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 68
 Daisy Chaining method

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 69
 Daisy Chaining method

Advantages –
1. Simplicity and Scalability.
2. The user can add more devices anywhere along the chain

Disadvantages –
3. The value of priority assigned to a device is depends on the
position of master bus.
4. Propagation delay is arises in this method.
5. If one device fails then entire system will stop working.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 70
 Polling or Rotating Priority Method

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 71
 Polling or Rotating Priority Method

Advantages –
1. This method does not favor any particular device and
processor.
2. The method is also quite simple.
3. If one device fails then entire system will not stop working.

Disadvantages –
4. Adding bus masters is difficult as increases the number of
address lines of the circuit.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 72
 Fixed priority or Independent Request
method

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 73
 Fixed priority or Independent Request
method
Advantages –
•This method generates fast response.

Disadvantages –
•Hardware cost is high as large no. of control lines are required.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 74
 Daily Quiz
1. To resolve the clash over the access of the system BUS we use ______
a) Multiple BUS
b) BUS arbitrator
c) Priority access
d) None of the mentioned
2. The device which is allowed to initiate data transfers on the BUS at any time is
called _____
a) BUS master
b) Processor
c) BUS arbitrator
d) Controller
3. ______ BUS arbitration approach uses the involvement of the processor.
a) Centralised arbitration
b) Distributed arbitration
c) Random arbitration
d) All of the mentioned

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 75

 Daily Quiz with Answers
1. To resolve the clash over the access of the system BUS we use ______
a) Multiple BUS
b) BUS arbitrator
c) Priority access
d) None of the mentioned
2. The device which is allowed to initiate data transfers on the BUS at any time is
called _____
a) BUS master
b) Processor
c) BUS arbitrator
d) Controller
3. ______ BUS arbitration approach uses the involvement of the processor.
a) Centralised arbitration
b) Distributed arbitration
c) Random arbitration
d) All of the mentioned

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 76

 Daily Quiz
4. When the processor receives the request from a device, it responds by sending
_____
a) Request signal
b) BUS grant signal
c) Response signal
d) None of the mentioned
5. Once the BUS is granted to a device ___________
a) It activates the BUS busy line
b) Performs the required operation
c) Raises an interrupt
d) All of the mentioned
6. After the device completes its operation _____ assumes the control of the BUS.
a) Another device
b) Bus Master
c) High Priority Device
d) None of the mentioned

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 77

 Daily Quiz with Answers
4. When the processor receives the request from a device, it responds by sending
_____
a) Request signal
b) BUS grant signal
c) Response signal
d) None of the mentioned
5. Once the BUS is granted to a device ___________
a) It activates the BUS busy line
b) Performs the required operation
c) Raises an interrupt
d) All of the mentioned
6. After the device completes its operation _____ assumes the control of the BUS.
a) Another device
b) Bus Master
c) High Priority Device
d) None of the mentioned

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 78

 Daily Quiz
7. The BUS busy line is used __________
a) To indicate the processor is busy
b) To indicate that the BUS master is busy
c) To indicate the BUS is already allocated
d) None of the mentioned

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 79

 Daily Quiz with Answers
7. The BUS busy line is used __________
a) To indicate the processor is busy
b) To indicate that the BUS master is busy
c) To indicate the BUS is already allocated
d) None of the mentioned

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 80

 Recap
• Bus arbitration refers to the process by which the current bus master
accesses and then leaves the control of the bus and passes it to the
another bus requesting processor unit.

• There are two approaches to bus arbitration: Centralized and Distributed

• There are three arbitration schemes which run on centralized arbitration

– Daisy chain, Polling and Independent request

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 81

 Introduction to Topic 4

Name of Topic Objective of Topic Mapping with CO

Register, bus and Students will be able
memory transfer. to know transfer CO 1
between the
registers, bus and
memory transfer

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 82

 Logic Gates
Multiplexer (MUX)
• It is a combinational circuit that has maximum of 2n data inputs, ‘n’
selection lines and single output line.
• One of these data inputs will be connected to the output based on the
values of selection lines.
• Multiplexers are also known as “Data n selector, parallel to serial
convertor, many to one circuit, universal logic circuit​”

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 83
 Logic Gates
Multiplexer (MUX)
• It is a combinational circuit that has maximum of 2n data inputs, ‘n’
selection lines and single output line.
• One of these data inputs will be connected to the output based on the
values of selection lines.
• Multiplexers are also known as “Data n selector, parallel to serial
convertor, many to one circuit, universal logic circuit​”

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 84
 Logic Gates
Multiplexer (MUX)
• It is a combinational circuit that has maximum of 2n data inputs, ‘n’
selection lines and single output line.
• One of these data inputs will be connected to the output based on the
values of selection lines.
• Multiplexers are also known as “Data n selector, parallel to serial
convertor, many to one circuit, universal logic circuit​”

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 85
 Logic Gates
Multiplexer (MUX)
• It is a combinational circuit that has maximum of 2n data inputs, ‘n’
selection lines and single output line.
• One of these data inputs will be connected to the output based on the
values of selection lines.
• Multiplexers are also known as “Data n selector, parallel to serial
convertor, many to one circuit, universal logic circuit​”

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 86
 Logic Gates
Multiplexer (MUX)
• It is a combinational circuit that has maximum of 2n data inputs, ‘n’
selection lines and single output line.
• One of these data inputs will be connected to the output based on the
values of selection lines.
• Multiplexers are also known as “Data n selector, parallel to serial
convertor, many to one circuit, universal logic circuit​”

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 87
 Logic Gates
Multiplexer (MUX)
• It is a combinational circuit that has maximum of 2n data inputs, ‘n’
selection lines and single output line.
• One of these data inputs will be connected to the output based on the
values of selection lines.
• Multiplexers are also known as “Data n selector, parallel to serial
convertor, many to one circuit, universal logic circuit​”

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 88
 Logic Gates
Multiplexer (MUX)
• It is a combinational circuit that has maximum of 2n data inputs, ‘n’
selection lines and single output line.
• One of these data inputs will be connected to the output based on the
values of selection lines.
• Multiplexers are also known as “Data n selector, parallel to serial
convertor, many to one circuit, universal logic circuit​”

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 89
 Logic Gates
Multiplexer (MUX)
• It is a combinational circuit that has maximum of 2n data inputs, ‘n’
selection lines and single output line.
• One of these data inputs will be connected to the output based on the
values of selection lines.
• Multiplexers are also known as “Data n selector, parallel to serial
convertor, many to one circuit, universal logic circuit​”

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 90
 Logic Gates
Multiplexer (MUX)
• It is a combinational circuit that has maximum of 2n data inputs, ‘n’
selection lines and single output line.
• One of these data inputs will be connected to the output based on the
values of selection lines.
• Multiplexers are also known as “Data n selector, parallel to serial
convertor, many to one circuit, universal logic circuit​”

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 91
 Multiplexer
Multiplexer (MUX)
• It is a combinational circuit that has maximum of 2n data inputs, ‘n’
selection lines and single output line.
• One of these data inputs will be connected to the output based on the
values of selection lines.
• Multiplexers are also known as “Data n selector, parallel to serial
convertor, many to one circuit, universal logic circuit​”

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 92
 4x1 Multiplexer
4x1 Multiplexer
• 4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 &
s0 and one output Y.
• The block diagram of 4x1 Multiplexer is shown in the following figure.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 93
 4x1 Multiplexer
• One of these 4 inputs will be connected to the output based on the
combination of inputs present at these two selection lines.

• Truth table of 4x1 Multiplexer is shown below.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 94
 4x1 Multiplexer
• From Truth table, we can directly write the Boolean function for output, Y
as

• This Boolean function can be implemented using Inverters, AND gates &
OR gate. The circuit diagram of 4x1 multiplexer is shown in the following
figure.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 95
 De-Multiplexer
De-Multiplexer (De-MUX)
• It is a combinational circuit that performs the reverse operation of
Multiplexer.
• It has single input, ‘n’ selection lines and maximum of 2n outputs.
• The input will be connected to one of these outputs based on the
values of selection lines.
• They are also known as “Data distributor, serial to parallel convertor,
one to many circuit”

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 96
 1x4 De-Multiplexer
1x4 De-Multiplexer
• 1x4 De-Multiplexer has one input I, two selection lines, s 1 & s0 and four
outputs Y3, Y2, Y1 &Y0.
• The block diagram of 1x4 De-Multiplexer is shown in the following
figure.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 97
 1x4 De-Multiplexer
• The single input ‘I’ will be connected to one of the four outputs, Y 3 to
Y0 based on the values of selection lines s1 & s0.
• The Truth table of 1x4 De-Multiplexer is shown below.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 98
 1x4 De-Multiplexer
• From the above Truth table, we can directly write the Boolean
functions for each output as

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 99
 1x4 De-Multiplexer
• These Boolean functions are implemented using Inverters & 3-input
AND gates.
• The circuit diagram of 1x4 De-Multiplexer is shown in the following
figure.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 100
 Decoder
• The Decoder is a combinational circuit that has ‘n’ input lines and
maximum of output lines.
• One of these outputs will be active High based on the combination of
inputs present, when the decoder is enabled.
• That means decoder detects a particular code.
• The outputs of the decoder are nothing but the min terms of ‘n’ input
variables lines, when it is enabled.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 101
 2 to 4 Decoder
• Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 &
Y0.
• The block diagram of 2 to 4 decoder is shown in the following figure.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 102
 2 to 4 Decoder
• One of these four outputs will be ‘1’ for each combination of inputs when
enable, E is ‘1’.
• The Truth table of 2 to 4 decoder is shown below-

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 103
 2 to 4 Decoder
• From Truth table, the Boolean functions for each output is

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 104
 2 to 4 Decoder
• The circuit diagram of 2 to 4 decoder is shown in the following figure

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 105
 Encoder
• An Encoder is a combinational circuit that performs the reverse
operation of Decoder.
• It has maximum of 2n input lines and ‘n’ output lines.
• It will produce a binary code equivalent to the input, which is active
High.
• Therefore, the encoder encodes 2n input lines with ‘n’ bits. It is optional
to represent the enable signal in encoders.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 106
 4 to 2 Encoder
• Let 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 &
A 0.
• The block diagram of 4 to 2 Encoder is shown in the following figure.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 107
 4 to 2 Encoder
• At any time, only one of these 4 inputs can be ‘1’ in order to get the
respective binary code at the output.
• The Truth table of 4 to 2 encoder is shown below

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 108
 4 to 2 Encoder
• From Truth table, the Boolean functions for each output is

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 109
 4 to 2 Encoder
• We can implement the above two Boolean functions by using two input
OR gates.
• The circuit diagram of 4 to 2 encoder is shown in the following figure

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 110
 HALF ADDER
• Half Adder is a combinational logic circuit.
• It is used for the purpose of adding two single bit numbers.
• It contains 2 inputs and 2 outputs (sum and carry).

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 111
 HALF ADDER
Limitation of Half Adder-

• Half adders have no scope of adding the carry bit resulting from the
addition of previous bits.
• This is a major drawback of half adders.
• This is because real time scenarios involve adding the multiple
number of bits which can not be accomplished using half adders.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 112
 FULL ADDER
• Full Adder is a combinational logic circuit.
• It is used for the purpose of adding two single bit numbers
with a carry.
• Thus, full adder has the ability to perform the addition of
three bits.
• Full adder contains 3 inputs and 2 outputs (sum and carry) as
shown-

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 113
 FULL ADDER

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 114
 FULL ADDER
• Full Adder is a combinational logic circuit.
• It is used for the purpose of adding two single bit numbers
with a carry.
• Thus, full adder has the ability to perform the addition of
three bits.
• Full adder contains 3 inputs and 2 outputs (sum and carry) as
shown-

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 115
 HALF SUBTRACTOR
• Half Subtractor is a combinational logic circuit.
• It is used for the purpose of subtracting two single bit
numbers.
• It contains 2 inputs and 2 outputs (difference and borrow).

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 116
 HALF SUBTRACTOR
• Half Subtractor is a combinational logic circuit.
• It is used for the purpose of subtracting two single bit
numbers.
• It contains 2 inputs and 2 outputs (difference and borrow).

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 117
 FULL SUBTRACTOR
• Full Subtractor is a combinational logic circuit.
• It is used for the purpose of subtracting two single bit
numbers.
• It also takes into consideration borrow of the lower significant
stage.
• Thus, full subtractor has the ability to perform the subtraction
of three bits.
• Full subtractor contains 3 inputs and 2 outputs (Difference
and Borrow) as shown-

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 118
 FULL SUBTRACTOR

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 119
 FULL SUBTRACTOR

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 120
 Register, bus and memory transfer
Register
• They are used to quickly accept, store, and transfer data and
instructions that are being used immediately by the CPU.
• They are used to hold the temporary data.
• There are various types of Registers those are used for various purpose.
Register Numbe Register Register Function
Symbol r of bits Name
DR 16 Data register Holds memory operands
AR 12 Address register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction register Holds instruction code
PC 12 Program counter Holds address of instruction
TR 16 Temporary register Holds temporary data
INPR 8 Input register Holds input character
OUTR 8 Output register Holds output character

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 121
 Register, bus and memory transfer
Register
• Computer registers are designated by capital letters (sometimes
followed by numerals) to denote the function of the register.
• The register that holds an address for the memory unit is memory
address register and is designated by the name MAR.
• The program counter register is called PC, IR is the instruction
register and R1 is a processor register

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 122
 Register, bus and memory transfer

Register Transfer
• Information transfer from one register to another is designated in
symbolic form by means of a replacement operator.
• R2 R1
• It denotes a transfer of the content of register R1 into register R2. It
designates a replacement of the content of R2 by the content of R1
without changing the content of R1 after transfer.
• If the Register transfer is to occur only under a predetermined control
condition, this can be shown by means of an if-then statement.

• If (P = 1) then (R2 R1)

• P: R2 R1,
where P is a control function that can be either 0 or 1

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 123
 Register, bus and memory transfer

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 124
 Register, bus and memory transfer

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 125
 Register, bus and memory transfer

Bus transfer
• A bus structure consists of a set of common lines, one for each bit of
a register.
• Control signals determine which register is selected by the bus during
each transfer.
• Multiplexers can be used to construct a common bus.
• Multiplexers select the source register whose binary information is
then placed on the bus.
• The select lines are connected to the selection inputs of the
multiplexers and choose the bits of one register

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 126
 Register, bus and memory transfer
Bus system for 4 registers

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 127
 Register, bus and memory transfer

Functional table for bus

S1 S0 REGISTER
SELECTED
0 0 A
0 1 B
1 0 C
1 1 D

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 128
 Register, bus and memory transfer

• In general, a bus system will multiplex k registers of n bits each to

produce an n- line common bus.
• This requires n multiplexers – one for each bit
• The size of each multiplexer must be k x 1
• Transfer of information from the bus to one of many destination
registers can be accomplished by connecting bus lines to the
inputs of all designation registers and activating the load control
of particular destination register selected.
• Symbolic statement-
• BUS C, R1 BUS,
• If bus is known to exist in the system, R1 C

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 129
 Bus Transfer using Three state buffer

• Instead of using multiplexers, three-state gates can be used to

construct the bus system
• A three-state gate is a digital circuit that exhibits three states.
• Two of the states are signals equivalent to logic 1 and 0
• The third state is a high-impedance state – this behaves like an open
circuit, which means the output is disconnected and does not have a
logic significance.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 130
 Bus Transfer using Three state buffer

• The three-state buffer gate has a normal input and a control input
which determines the output state.
• With control 1, the output equals the normal input
• With control 0, the gate goes to a high-impedance state
• This enables a large number of three-state gate outputs to be
connected with wires to form a common bus line without endangering
loading effects

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 131
 Bus Transfer using Three state buffer

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 132
 Bus Transfer using Three state buffer

• Decoders are used to ensure that no more than one control input is
active at any given time
• This circuit can replace the multiplexer.
• To construct a common bus for four registers of n bits each using
three-state buffers, we need n circuits with four buffers in each
• Only one decoder is necessary to select between the four registers

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 133
 Memory Transfer
Most of the standard notations used for specifying operations on
memory transfer are stated below.

• The transfer of information from a memory unit to the user end is

called a Read operation.
• A memory word is designated by the letter M.
• We must specify the address of memory word while writing the
memory transfer operations.
• The address register is designated by AR and the data register by DR.
• Thus, a read operation can be stated as:
Read: DR ← M [AR]
• The Read statement causes a transfer of information into the data
register (DR) from the memory word (M) selected by the address
register (AR).

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 134
 Memory Transfer

• The transfer of new information to be stored in the memory is called

a Write operation.
• The Write statement causes a transfer of information from register
R1 into the memory word (M) selected by address register (AR).
• Write: M [AR] ← R1

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 135
 Memory Transfer

Memory Transfer Block diagram

Above Diagram showing connections to memory unit.

Write: M[AR] ← DR
Read: DR ← M[AR]

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 136
 Daily Quiz
1. The transfer of information from a memory unit to the user end is called
a _______operation.
2. _________ are used to quickly accept, store, and transfer data and
instructions that are being used immediately by the CPU.
3. A decoder converts n inputs to __________ outputs. ()
4. Which of the following are building blocks of encoders?
a) NOT gate
b) OR gate
c) AND gate
d) NAND gate
5. The transfer of new information to be stored in the memory is called
a _______ operation.
6. Which of the following can be represented for decoder?
a) Sequential circuit
b) Combinational circuit
c) Logical circuit
d) None of the mentioned
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 137
 Daily Quiz with Answers
•

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 138

 Recap
• Registers are used to quickly accept, store, and transfer data and
instructions that are being used immediately by the CPU.
• Multiplexers can be used to construct a common bus.
• A three-state gate is a digital circuit that exhibits three states – 0,1 and
high impedance state.
• The transfer of information from a memory unit to the user end is called
a Read operation.
• The transfer of new information to be stored in the memory is called
a Write operation.

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 139

 Introduction to Topic 5

Name of Topic Objective of Topic Mapping with CO

Processor Students will be able
organization, General to know various CO 1
register organization process organization
and stack and data stored in
organization register and stack

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 140

 Registers

• Registers are used to store data temporarily.

Registers

User Visible Register Control & Status Register

1. General Purpose Register

1. Program counter
2. Data Register
2. Instruction register
3. Address Register
3. MAR
4. Condition codes
4. MDR

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 141
 Processor organization

• Processor organization means how the components of processor are

connected and accomplish their task.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 142
 Processor organization-General register
organization
Most computers fall into one of three types of CPU organizations:
• Single accumulator organization.
• General register organization.
• Stack organization.

1. Single accumulator organization

• The instruction format in this type of computer uses one address field.
• All operations are performed with an implied accumulator register.
• Example : ADD X

• where X is the address of the operand. The ADD instruction in this case
results in the operation AC <--AC + M[X].
• AC is the accumulator register and M[X] symbolizes the memory word
located at address X.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 143
 Processor organization

2. General register organization

• The instruction format in this type of computer needs three register

address fields.
• ADD R1, R2, R3 to denote the operation R 1 <---R2 + R3 .
• ADD R1, R2, would denote the operation R 1 <---R1 + R2. Only register
addresses for R 1 and R2 need be specified in this instruction.
• General register-type computers employ two or three address fields in
their instruction format.
• Each address field may specify a processor register or a memory word.
• ADD R1, X
R1 ---- R1 + M [X]

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 144
 Processor organization
3. Stack organization

• The stack-organized CPU ,Computers with stack organization would

have PUSH and POP instructions which require an address field. Thus
the instruction
• PUSH X
It will push the word at address X to the top of the stack. Stack pointer
is updated automatically.

• ADD
This instruction in stack computer consists of an operation code only
with no address field.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 145
 General register organization

General registers organization

• In this type of organization, computer uses two or three address fields in
their instruction format.

• Each address field may specify a general register or a memory word. If

many CPU registers are available for heavily used variables and
intermediate results

For example:
• MULT R1, R2, R3
• This is an instruction of an arithmetic multiplication written in assembly
language. It uses three address fields R1, R2 and R3.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 146
 General register organization
• The meaning of this instruction is:
R1 <-- R2 * R3

• This instruction also can be written using only two address fields as:
MULT R1, R2

• In this instruction, the destination register is the same as one of the

source registers. This means the operation
R1 <-- R1 * R2
• The use of large number of registers results in short program with
limited instructions.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 147
 General register organization

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 148
 General register organization

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 149
 Encoding of Register Selection Fields
Binary Code SELA SELB SELD

000 INPUT INPUT NONE

001 R1 R1 R1

010 R2 R2 R2

011 R3 R3 R3

100 R4 R4 R4

101 R5 R5 R5

110 R6 R6 R6

111 R7 R7 R7

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 150
 Encoding of ALU Operations
OPR Select Operation Symbol

00000 Transfer A TSFA

00001 Increment A INCA

00010 Add A + B ADD

00101 Subtract A - B SUB

00110 Decrement A DECA

01000 AND A and B AND

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 151
 Example of Microoperations

Subtract microoperation:
R1 ----- R2 – R3

Binary control word for subtract microoperation-

Field: SELA SELB SELD OPR

Symbol: R2 R3 R1 SUB

Control word: 010 011 001 00101

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 152
 General register organization

• The control unit that operates the CPU bus system directs the
information flow through the registers and ALU by selecting the
various components in the system. For example, to perform the
operation
• R1 <--R2 + R3. The control must provide binary selection variables to
the following selector inputs:
1. MUX A selector (SELA): to place the content of R2 into bus A .
2. MUX B selector (SELB): to place the content o f R 3 into bus B .
3. ALU operation selector (OPR): to provide the arithmetic addition
A+B.
• Decoder destination selector (SELD): to transfer the content of the
output bus into R 1 .

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 153
 General register organization

The advantages of General register based CPU organization

• Efficiency of CPU increases as there are large number of registers are

used in this organization.

• Less memory space is used to store the program since the instructions
are written in compact way.

The disadvantages of General register based CPU organization

• Care should be taken to avoid unnecessary usage of registers. Thus,
compilers need to be more intelligent in this aspect.

• Since large number of registers are used, thus extra cost is required in
this organization.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 154
 Stack Organization
• A stack is a storage device that stores information in such a manner
that the item stored last is the first item retrieved.
• The stack in digital computers is essentially a memory unit with an
address register that can count only. The register that holds the
address for the stack is called a stack pointer (SP) because its value
always points at the top item in the stack.
• The physical registers of a stack are always available for reading or
writing. It is the content of the word that is inserted or deleted.

Register stack:

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 155
 Stack Organization

PUSH:

• If the stack is not full (FULL =0), a new item is inserted with a push
operation. The push operation consists of the following sequences of
micro operations:

SP ← SP + 1 Increment stack pointer

M [SP] ← DR WRITE ITEM ON TOP OF THE STACK

IF (SP = 0) then (FULL ← 1) Check is stack is full

EMTY ← 0 Mark the stack not empty

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 156

 Stack Organization

POP:
• A new item is deleted from the stack if the stack is not empty (if
EMTY = 0). The pop operation consists of the following sequences of
micro operations:

DR ← M [SP] Read item on top of the stack

SP ← SP - 1 Decrement stack pointer
IF (SP = 0) then (EMTY ← 1) Check if stack is empty
FULL ← 0 Mark the stack not full

• The top item is read from the stack into DR. The stack pointer is
then decremented. If its value reaches zero, the stack is empty, so
EMTY is set to 1.

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 157

 Stack Organization
Memory Stack

• The implementation of a stack

in the CPU is done by
assigning a portion of
memory to a stack operation
and using a processor register
as a stack pointer.

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 158

 Stack Organization

Memory Stack

• The program counter PC points at the address of the next instruction in

the program which is used during the fetch phase to read an instruction.

• The address registers AR points at an array of data which is used during

the execute phase to read an operand.

• The stack pointer SP points at the top of the stack which is used to push
or pop items into or from the stack.

• The three registers are connected to a common address bus, and either
one can provide an address for memory.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 159
 Stack Organization

PUSH
• A new item is inserted with the push operation as follows:
SP ← SP - 1
M[SP] ← DR
• The stack pointer is decremented so that it points at the address
of the next word.
• A memory write operation inserts the word from DR into the top
of the stack.
POP
• A new item is deleted with a pop operation as follows:
DR ← M[SP]
SP ← SP + 1

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 160
 Stack Organization
Polish Notation
• A stack organization is very effective for evaluating arithmetic
expressions. The common arithmetic expressions are written in infix
notation, with each operator written between the operands.

• Consider the simple arithmetic expression

A•B + C•D

A + B Infix notation
+AB Prefix or Polish notation
AB+ Postfix or reverse Polish notation (RPN)

• The reverse Polish notation is in a form suitable for stack

manipulation.
• The expression A•B + C•D is written in reverse Polish notation as
AB•CD•+
Swarnima Logic Design & Computer Architecture Unit 1
08/09/2025 161
 Daily Quiz
1. The Stack follows the sequence
a) first-in-first-out
b) first-in-last-out
c) last-in-first-out
d) last-in-last-out
2. The process of storing the data in the stack is called ……… the stack.
a) pulling into
b) pulling out
c) pushing into
d) popping into
3. The stack is useful for
a) storing the register status of the processor
b) temporary storage of data
c) storing contents of registers temporarily inside the CPU
d) all of the mentioned

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 162

 Daily Quiz
4. The reverse process of transferring the data back from the stack to the
CPU register is known as
a) pulling out the stack
b) pushing out the stack
c) popping out the stack
d) popping off the stack
5. Which of the following is not a visible register?
a) General Purpose Registers
b) Address Register
c) Status Register
d) MAR
6. Opcode indicates the operations to be performed.
a) True
b) False

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 163

 Introduction to Topic 7

Name of Topic Objective of Topic Mapping with CO

Addressing Modes Students will be able
to know the different CO 1
addressing modes.

08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1 164

 Addressing Modes

• The addressing mode specifies a rule for interpreting or modifying the

address field of the instruction before the operand is actually
referenced.
• The decoding step in the instruction cycle determines the operation to
be performed, the addressing mode of the instruction, and the location
of the operands

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 165
 Addressing Modes
1. Implied mode:
• The operands are specified implicitly in the definition of the instruction –
complement accumulator or zero-address instructions.
• CMA , CLC

2. Immediate mode:
• The operands value are specified in the instruction.
• Immediate mode instructions is said to be useful for initializing registers
to a constant value.
• MOV AL, 35 H

3. Register mode:
• The operands are in registers and the register is present in CPU.
• The data is in the register that is specified by the instruction.
• MOV A,C (move the content of C register to A register)

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 166
 Addressing Modes
Register Register Indirect
Addressing Addressing

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 167
 Addressing Modes
4. Register Indirect mode:
• In this mode the instruction specifies a register in the CPU whose contents
give the address of the operand in memory.
• The selected register contains the address of the operand rather than the
operand itself.
• MOV AX,[CX] (move the content of memory location addressed by the
register CX to the register AX)

5. Autoincrement/Autodecrement mode:
• This is similar to register indirect mode except that the register is
incremented or decremented after or before its value is used to access
memory.
a) Increment mode- After accessing the operand the contents of this
register are automatically incremented to point to next consecutive
memory location.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 168
 Addressing Modes
Example: Add R1, (R2+)
OR
R1 = R1 + M[R2]
R2 = R2 + d

Useful for stepping through arrays in a loop.

R2 – start of the array, d- size of an element.

b) Decrement Mode:
• Before accessing the operand , the contents of this register are
automatically decremented to point to the previous consecutive memory
location.
Example- Add R1, (-R2)
OR
R2 = R2 – d
R1 = R1Swarnima
+ M [R2]Logic Design & Computer Architecture Unit 1
08/09/2025 169
 Addressing Modes
6. Direct Address mode:
• In this mode the effective address is equal to the address part of the
instruction.
• The operand resides in memory and its address is given directly by the
address field of the instruction.
• Example – ADD AL, [0301] (add the content of address 0301 to A)

7. Indirect Address mode :

• In this mode the address field of the instruction gives the address where
the effective address is stored in memory.
• In this address field of instruction gives the address where the effective
address is stored in memory.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 170
 Addressing Modes

Direct Addressing Indirect

Addressing

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 171
 Addressing Modes

• Relative address mode: the effective address is the summation of the

address field and the content of the PC
• Indexed addressing mode: the effective address is the summation of an
index register and the address field
• Base register address mode: the effective address is the summation of
a base register and the address field

• effective address = address part of instruction + content of CPU

register

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 172
 Daily Quiz
1. RTL stands for:
a. Random transfer language
b. Register transfer language
c. Arithmetic transfer language
d. All of these
2. The register that includes the address of the memory unit is termed as
the :
a. MAR
b. PC
c. IR
d. None of these
3. Which are the operation that a computer performs on data that put in
register:
a. Register transfer
b. Arithmetic
c. Logical
d. All of these,,,, 173
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 Daily Quiz
4. Which operation puts memory address in memory address register and
data in DR:
a. Memory read
b. Memory write
c. Both
d. None

5. A stack organized computer uses instruction of

a. Indirect addressing
b. Two addressing
c. Zero addressing
d. Index addressing

174
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 Daily Quiz
6. A flip flop is a binary cell capable of storing information of
a. One bit
b. One byte
c. Zero bit
d. Eight bits

7. To resolve the clash over the access of the system BUS we use ______
a. Multiple BUS
b. BUS arbitrator
c. Priority access
d. None of the mentioned

175
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 Daily Quiz

8. The device which is allowed to initiate data transfers on the BUS at any
time is called _____
a. BUS master
b. Processor
c. BUS arbitrator
d. Controller

176
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 Weekly Assignment

1. Convert the following arithmetic expressions from infix to reverse

polish notation

a) A*B+C*D+E*F

b) A* (B+C*CD+E)/F*(G+H)

2. Define System Bus. What are different bus structures?

3. What is general register organization?

4. Explain the various addressing modes with example.

5. What do you mean by processor organization? Explain various types of
processor organization

177
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 Weekly Assignment
1. A digital computer has a common bus system for 16 registers of 32 bits
each. The bus is constructed with multiplexers.
a) How many multiplexers are there in the bus?
b) What size of multiplexers are needed?
c) How many selection inputs are there in each multiplexer?
2. Draw basic functional units of a computer with interconnection.
3. Draw a block diagram of 64 word Register stack and write sequence of
microoperations for PUSH and POP operation.
4. Discuss the advantages and disadvantages of Daisy Chain and Polling
bus arbitration schemes.
5. What is control word? Specify the control word for subtract
microoperation given in the statement –
R1 ------ R2 – R3

178
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 Topic Links
1. Types OF Buses-
[Link]
G6QNKq53C6oNXGrX&index=4
2. Common bus system using multiplexer
[Link]
G6QNKq53C6oNXGrX&index=5
3. Single Accumulator CPU Organisation
[Link]
G6QNKq53C6oNXGrX&index=15
4. General Register CPU Organisation
[Link]
6QNKq53C6oNXGrX&index=16
5. Register Stack Organisation
[Link]
6QNKq53C6oNXGrX&index=17

179
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 MCQ
1. To resolve the clash over the access of the system BUS we use______
a) Multiple BUS b) BUS arbitrator
c) Priority access d) None of the mentioned

2. The device which is allowed to initiate data transfers on the BUS at

any time is called _____
a) BUS master b) Processor
c) BUS arbitrator d) Controller

3. ______ BUS arbitration approach uses the involvement of the

processor.
a) Centralized arbitration b) Distributed arbitration
c) Random arbitration d) All of the mentioned

180
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 MCQ

4. When the processor receives the request from a device, it responds

by sending _____
a) Acknowledge signal b) BUS grant signal
c) Response signal d) None of the mentioned

5. In Centralized Arbitration ______ is/are is the BUS master.

a) Processor b) DMA controller
c) Device d) Both Processor and DMA controller

6. Once the BUS is granted to a device ___________

a) It activates the BUS busy line b) Performs the required operation
c) Raises an interrupt d) All of the mentioned

181
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 MCQ
7. In Distributed arbitration, the device requesting the BUS ______
a) Asserts the Start arbitration signal b) Sends an interrupt signal
c) Sends an acknowledge signal d) None of the mentioned

8. How is a device selected in Distributed arbitration?

a) By NANDing the signals passed on all the 4 lines
b) By ANDing the signals passed on all the 4 lines
c) By ORing the signals passed on all the 4 lines
d) None of the mentioned

9. If two devices A and B contesting for the BUS have ID’s 5 and 6
respectively, which device gets the BUS based on the Distributed
arbitration.
a) Device A b) Device B
c) Insufficient information d) None of the mentioned

182
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 MCQ
10. During the execution of a program which gets initialized first?
a) MDR b) IR
c) PC d) MAR

11. Which of the register/s of the processor is/are connected to Memory

Bus?
a) PC b) MAR
c) IR d) Both PC and MAR

12. ISP stands for _________

a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
d) Interrupt Service Procedure

183
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 MCQ
13. The addressing mode, where you directly specify the operand value is
_______
a) Immediate b) Direct
c) Definite d) Relative

14. _____ addressing mode is most suitable to change the normal

sequence of execution of instructions.
a) Relative b) Indirect
c) Index with Offset d) Immediate

15. ______ is generally used to increase the apparent size of physical

memory.
a) Secondary memory b) Virtual memory
c) Hard-disk d) Disks

184
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 Glossary Questions
A typical digital computer has many registers, and paths must be
provided to transfer information from one register to another. The
number of wires will be excessive if separate lines are used between
each register and all other registers in the system. A more efficient
scheme for transferring information between registers in a multiple-
register configuration is a common bus system. A bus structure consists
of a set of common lines, one for each bit of a register, through which
binary information is transferred one at a time. Control signals determine
which register is selected by the bus during each particular register
transfer. One way of constructing a common bus system is with
multiplexers. The multiplexers select the source register whose binary
information is then placed on the bus.

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 185
 Glossary Questions
1. Construct a bus system for four registers with help of multiplexers.
2. A digital computer has a common bus system for 16 registers of 32
bits each. The bus is constructed with multiplexers.
a) How many selection inputs are there in each multiplexer?
b) What size of multiplexers are needed?
c) How many multiplexers are there in the bus?
3. What is Multiplexer?

Swarnima Logic Design & Computer Architecture Unit 1

08/09/2025 186
 Old Question Papers - Sessional
Sessional 1

Sessional 1

Sessional 2

Sessional 3

187
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 Noida Institute of Engineering and Technology, GR. Noida
(An Autonomous Institute)
School of Computer Science & Engineering in Emerging
Technologies

Introduction

Unit: 1

Logic Design & Computer

Swarnima
Architecture (ACSAI0302)
Assistant Professor
B Tech (AIML)- 3rd Sem NIET, Greater Noida

Swarnima Logic Design & Computer Architecture Unit 1

188
08/09/2025
 Old Question Papers

2018-19

2019-20

189
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 Expected Questions
1. Explain different addressing modes.
2. Explain the importance of different addressing modes in computer
architecture with suitable example.
3. What is an instruction format? Explain different types of instruction
formats in detail.
4. A digital computer has a common bus system for 16 register of 32 bits
each. The bus is Constructed with multiplexers.
(i) How many selection inputs are there in each multiplexer?
(ii) What sizes of multiplexers are needed?
(iii) How many multiplexers are there in the bus?
5. Show the block diagram of the hardware that implements the following
register transfer statement: P: R2 <--- R1
6. Explain sequence of micro-operations for implementing PUSH and POP
instructions in the register stack.

190
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 Expected Questions
7. Differentiate between Computer Architecture and Computer
Organization Explain different addressing modes.
8. Draw the Distributed Arbitration interface circuit for two devices A and B
with their 4- bit unique ID 0110 and 0001 respectively.
i. Write down the new ID generated on Arbitration lines.
ii. Which device become Bus Master.
9. Convert the arithmetic expressions from infix to reverse polish notation.
i. A*B+C*D+E*F
ii. A+B/C-D+E
10. Explain bus organization for seven CPU registers with the help of block
diagram and control word.
11. Draw the block diagrams for Daisy chahing and Independent
Centralised Arbitration schemes.
12. Draw the Multiple Bus structures along with its advantage and
disadvantage.
191
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 Recap of Unit
• Computer Organization and Architecture provides in-depth knowledge
of internal working, structuring, and implementation of a computer
system
• Computer Architecture is concerned with the way hardware
components are connected together to form a computer system.
• Computer Organization is concerned with the structure and behaviour
of a computer system as seen by the user.
• A bus is a common pathway through which information flows from one
computer component to another.
• Types of Computer BUS: Data Bus ,Address Bus, Control Bus
• Bus Arbitration -It refers to the process by which the current bus master
accesses and then leaves the control of the bus and passes it to the
another bus requesting processor unit.

192
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 Recap of Unit
• There are two approaches to bus arbitration: Centralized and
Distributed
• There are three arbitration schemes which run on centralized
arbitration – Daisy chain, Polling and Independent request.
• Registers are used to quickly accept, store, and transfer data and
instructions that are being used immediately by the CPU.
• Multiplexers can be used to construct a common bus.
• A three-state gate is a digital circuit that exhibits three states – 0,1 and
high impedance state.
• The transfer of information from a memory unit to the user end is called
a Read operation.
• The transfer of new information to be stored in the memory is called
a Write operation.

193
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1
 Recap of Unit
• Most computers fall into one of three types of CPU organizations:
1. Single accumulator organization.
2. General register organization.
3. Stack organization

• Addressing modes- Implied mode, immediate addressing mode,

register addressing mode, register indirect addressing mode, direct
addressing mode, indirect addressing mode,
autoincrement/autodecrement mode, relative addressing mode, base
addressing mode, indexed addressing mode

194
08/09/2025 Swarnima Logic Design & Computer Architecture Unit 1