CPE 519

Digital Design with VHDL

Basic Language Elements

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 1

Basic elements of the language
• These include
• data objects that store values of a given type,
• literals that represent constant values, and
• operators that operate on data objects.
• Every data object belongs to a specific type.
• Identifiers (Naming and labelling)
• An identifier in VHDL is composed of a sequence of one or more characters.
Rule of Thumb:
1. All names should start with an alphabet character (a-z or A-Z)
2. Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_)
3. Do not use any punctuation or reserved characters within a name (!, ?,
., &, +, -, etc.)
4. Do not use two or more consecutive underscore characters (__) within
a name (e.g., Sel__A is invalid)
5. All names and labels in a given entity and architecture must be unique

2
Identifiers and Data Objects
• Examples of Identifiers :
• serial_data, parallel_data, DRIVE_BUS, SelectSignal RAM_Address, SET_CK_HIGH
CONST32_59 r2d2
• VHDL is case insensitive. The following are equivalent
• databus
• Databus
• DataBus
• DATABUS

• Data Objects
• A data object holds a value of a specified type.
• It is created by means of an object declaration. An example is
• VARIABLE count: INTEGER;

• This results in the creation of a data object called count which can hold integer
values.

• The object count is also declared to be of variable class.

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 3
Data Objects…
• Every data object belongs to one of the following three classes:
1. Constant: An object of constant class can hold a single value. The value cannot
be changed during the course of the simulation.
2. Variable: An object of variable class can also hold a single value of a
given type. However in this case, different values can be assigned to the object at
different times using a variable assignment statement.
3. Signal: An object belonging to the signal class has
• a past history of values, a current value, and a set of future values.
• future values can be assigned to a signal object using a signal assignment statement.
4. File (cannot be synthesized)

• Related construct
• Alias

• Signal objects are typically used to model wires and flip-flops

• while variable and constant objects are typically used to model the
behaviour of the circuit
Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 4
Object Declarations and Assignment
• Constant Declarations
• CONSTANT rise_time: TIME := 10ns;
• CONSTANT bus_width: INTEGER := 8:

• Variable Declarations
• VARIABLE ctrl_status: BIT_VECTOR(10 DOWNTO 0);
• VARIABLE sum: integer RANGE 0 to 100 := 10;
• VARIABLE found, done: BOOLEAN

• Signal:
• Declarations
• SIGNAL clock: BIT;
• SIGNAL data_bus: BIT_VECTOR(0 to 7);
• SIGNAL gate_delay: TIME := 10 ns;
• Assignment
• SIGNAL_name <= projected_waveform;
• z <= a AND b;
Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 5
Alias
• Not an object
• Alternative name for an object
• Used to enhance readability

SIGNAL: word: STD_LOGIC_VECTOR (15 DOWNTO 0);

ALIAS op: STD_LOGIC_VECTOR (6 DOWNTO 0) IS word (15 DOWNTO 9);

ALIAS reg1: STD_LOGIC_VECTOR (2 DOWNTO 0) IS word (8 DOWNTO 6);

ALIAS reg2: STD_LOGIC_VECTOR (2 DOWNTO 0) IS word (5 DOWNTO 3);

ALIAS reg3: STD_LOGIC_VECTOR (2 DOWNTO 0) IS word (2 DOWNTO 0);

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 6

Data Types
• Data Types
• a set of values an object may assume and
• a set of operations that may be performed on objects of this data type.

• VHDL is a strongly-typed language

• an object can only be assigned with a value of its type
• only the operations defined with the data type can be performed on the
object

• VHDL data type classifications:

• Scalar: numeric (integer, floating-point and physical), enumeration and
physical objects
• Composite: Arrays (elements of a single type) and
Records (elements of different types)
• Access: Value sets that point to dynamic variables
• File: Collection of data objects outside the model
Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 7
Data Types: Subtypes
• Scalar data type: Certain scalar data types are predefined in a package called “std”
(standard) and do not require a type declaration statement.
• Examples:
• BOOLEAN (true, false)
• BIT (‘0’, ‘1’)
• INTEGER (-2147483648 to 2147483647)
• REAL (-1.0E38 to 1.0E38)
• CHARACTER (ASCII character set)
• TIME (-2147483647 to 2147483647)
• It is possible to derive restricted types, called subtypes, from other predefined or user-
defined types
• A subtype is a type with a constraint.
• The constraint specifies the subset of values for the type.
• The type is called the base type of the subtype.
• An object is said to belong to a subtype if it is of the base type and if it satisfies the constraint.
• Subtype declarations are used to declare subtypes. An object can be declared to either belong to
a type or to a subtype.
• Examples of subtypes are:
• SUBTYPE my_integer IS INTEGER RANGE 48 to 156 ;
• TYPE digit IS ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9') ;
• SUBTYPE middle IS digit RANGE '3' to '7' ;
Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 8
Scalar Types
• Integer types, floating point types, and physical types are classified as
numeric types since the values associated with these types are numeric.
• Enumeration and Integer types are called discrete types since these
types have discrete values associated with them.
• Every value belonging to an enumeration type, integer type, or a physical type has
a position number associated with it.
• This number is the position of the value in the ordered list of values belonging to that
type.
• Examples:
• Enumeration type:
• TYPE Micro_op IS (load, store, add, sub, mul, div);
• SUBTYPE Arith_op IS Micro_op RANGE Add to Div;
• Integer Types:
• type INDEX is range 0 to 15;
• type WORD_LENGTH is range 31 downto 0;
• Floating Point Types
• TYPE TTL_VOLTAGE IS RANGE -5.5 to -1.4;
• TYPE REAL_DATA IS RANGE 0.0 to 31.9;

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 9

Scalar Types…
• Physical Types:
• A physical type contains values that represent measurement of
some physical quantity, like time, length, voltage, and current.
• Values of this type are expressed as integer multiples of a base
unit.
• An example of a physical type declaration is
TYPE current IS RANGE 0 to 1 E9
UNITS
nA; -- (base unit)
nano-ampere
uA = 1000 nA; -- micro-ampere
mA = 1000 μA; --milli-ampere
Amp = 1000 mA; -- ampere
END UNITS;

SUBTYPE filter_current IS current RANGE 10 μA to 5 mA;

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 10

Composite
• Array Types
• An object of an array type consists of elements that have the same
type. Examples of array type declarations are

TYPE ADDRESS_WORD IS ARRAY (0 TO 63) OF BIT;

TYPE DATA_WORD IS ARRAY (7 DOWNTO 0) of MVL;
TYPE ROM IS ARRAY (0 TO 125) OF DATA_WORD;

• There are two predefined one-dimensional unconstrained array

types in the language, STRING and BIT_VECTOR.

• STRING is an array of characters while BIT_VECTOR is an array of

bits. Examples are
VARIABLE message: STRING(1 TO 17) := "Hello, VHDL world";
SIGNAL RX_BUS: BIT_VECTOR(0 TO 5) := O"37";

-- O"37" is a bit-string literal representing the octal value 37.

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 11
Composite…
• Record Types
• An object of a record type is composed of elements of
same or different types.
• It is analogous to the record data type in Pascal and the struct
declaration in C.
• An example of a record type declaration is
TYPE pin_type IS RANGE 0 TO 10;
TYPE MODULE is
RECORD
SIZE: INTEGER RANGE 20 TO 200;
critical_dly: TIME;
no_inputs: pin_type:
no_outputs: pin_type;
END RECORD

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 12

 Operators
• Object type also identifies the operations that may be performed on an object.
• The predefined operators in the language are classified into the following five categories:
1. Logical operators
2. Relational operators
3. Adding operators
4. Multiplying operators
5. Miscellaneous operators
• The operators have increasing precedence going from category (1) to (5).
• Operators in the same category have the same precedence and evaluation is done left to right.
• Parentheses may be used to override the left to right evaluation.

• Logical Operators: AND, OR, NAND, NOR, XOR, XNOR

• Relational Operators: =, /=, <, <=, >, >=
• Shift Operators: SLL, SRL, SLA, SRA, ROL, ROR
• Adding Operators: &, +, -
• Sign: +, -
• Multiplying Operators: *, /, MOD, REM
• Miscellaneous: **, ABS, NOT
• Not all these operators are synthesizable

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 13

Overloading
• Overloading: same operator of different data types
• Overloaded operators in std_logic_1164 package
• An example of overloading is the function “AND”.
SIGNAL result0, signal1, signal2 : std_logic;
SIGNAL result1 : std_logic_vector(31 DOWNTO 0);
SIGNAL signal3 : std_logic_vector(31 DOWNTO 0);
SIGNAL signal4 : std_logic_vector(31 DOWNTO 0);

BEGIN
result0 <= signal1 AND signal2; -- simple AND
result1 <= signal3 AND signal4; -- many ANDs
END;
Overloaded Data type Data type Data type
operator of operand a of operand b of resutl
NOT a std_logic_vector same as a
std_logic
a NOT b
a OR b
a xor b std_logic_vector same as a same as a
a NAND b std_logic
a NOR b
a XNOR b

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 14

Operators over an array data type
• Relational operators for array
• operands must have the same element type but their lengths
may differ
• Two arrays are compared element by element, from the left
most element
• All following returns true
• "011"="011", "011">"010", "011">"00010",
"0110">"011"
• Concatenation operator (&)
• e.g.,
y <= "00" & a(7 downto 2);
y <= a(7) & a(7) & a(7 downto 2);
y <= a(1 downto 0) & a(7 downto 2);

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 15

Array aggregate
• Aggregate is a VHDL construct to assign a value to an
array-typed object
• E.g.,
a <= "10100000";
a <= (7=>'1', 6=>'0', 5=>'1', 4=>'0', 3=>'0', 2=> ‘0’, 1=>'0', 0=>'0');
a <= (7|5=>'1', 6|4|3|2|1|0=>'0');
a <= (7|5=>'1', others=>'0’);
• E.g.,
a <= "00000000"
a <= (others=>'0');

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 16

VHDL Library
• A place to store the analyzed design units
• Normally mapped to a directory in host computer
• Software define the mapping between the symbolic library and physical
location
• Default library: “work”
• Library “ieee” is used for many ieee packages

• To facilitate the synthesis, IEEE has developed several VHDL packages, including
the std-logic-1164 package and the numeric-std package, which are defined in
IEEE standards 1164 and 1076.3
• Example:
LIBRARY ieee;
USE ieee.std_logic_vector_1164.all

• Line 1: invoke a library named ieee

• Line 2: makes std_logic_1164 package visible to the subsequent design units
• The package is normally needed for the std_logic/std_logic_vector data types

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 17

Library Declarations
Library declaration

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY nand_gate IS
PORT( Use all definitions from
a : IN STD_LOGIC; the package
b : IN STD_LOGIC; std_logic_1164
z : OUT STD_LOGIC);
END nand_gate;

ARCHITECTURE model OF
nand_gate IS
BEGIN
z <= a NAND b;
END model;
Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 18
Libraries…

• ieee
Specifies multi-level logic system,
including STD_LOGIC, and Need to be
STD_LOGIC_VECTOR data types explicitly
declared
• Std
Specifies pre-defined data types
(BIT, BOOLEAN, INTEGER, REAL,
SIGNED, UNSIGNED, etc.), arithmetic
operations, basic type conversion Visible by
functions, basic text i/o functions, etc. default

• Work
• Holds current designs after compilation

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 19

 BIT versus STD_LOGIC
STD_LOGIC Type

• BIT type can only have a value

of '0' or '1'
• STD_LOGIC can have nine values
• 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'
• Useful mainly for simulation
• '0', '1', 'Z', '-' are synthesizable
• `(your codes should contain only
these four values)

• The ’ L and ’H values are seldom used now

since current design practice rarely utilizes a
wired-logic circuit

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 20

STD_LOGIC Meanings
• ’ 0 ’ and ’ 1 ’ :
• stand for “forcing logic 0” and “forcing logic 1 ,” which mean that the signal is
driven by a circuit with a regular driving current.
• ‘Z ’ :
• stands for high impedance, which is usually encountered in a tri-state buffer.
• ’L’ and ‘H’:
• stand for “weak logic 0” and “weak logic 1,” which means that the signal is
obtained from wired-logic types of circuits, in which the driving current is
weak.
• ’ X ’ and ‘W’ :
• stand for “forcing unknown” and “weak unknown.” The unknown represents
that a signal reaches an intermediate voltage value that can be interpreted as
neither logic 0 or logic 1.
• ’U’ :
• `stands for uninitialized. It is used in simulation to indicate that a signal or
variable has not yet been assigned a value.
• ’-’:
• stands for don’t-care.
Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 21
STD_LOGIC Rules

• Use std_logic or std_logic_vector for all entity input or

output ports

• Do not use integer, unsigned, signed, bit for ports

• You can use them inside of architectures if desired

• You can use them in generics

• Instead use std_logic_vector and a conversion function

inside of your architecture

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 22

Resolving logic levels

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 23

Data types in the IEEE numeric-std package
• In addition to logical operations, digital hardware frequently
involves arithmetic operation as well.
• In VHDL and the std-logic-1164 package, the arithmetic operations
are defined only over the integer data type.
• To perform addition of the a and b signals, we must use the integer
data type, as in
signal a, b, sum: integer;
...
sum <= a + b;

• Problem with the above code:

• the code doesn’t indicate the range (number of bits) of the a and b signals
• Cannot be Synthesised but can be Simulated.
• Difficult to synthesise since there is a huge difference b/w the HW complexity
of an 8-bit adder and that of a 32-bit adder

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 24

IEEE numeric-std: Unsigned or Signed Number
• A better alternative is to use an array of 0’s and 1’s and interpret it as an
unsigned or signed number.
• We can define the width of the input and the size of the adder precisely, and
thus have better control over the underlying hardware.
• The IEEE numeric-std package was developed for this purpose.
• IEEE numeric_std package: define integer as a an array of elements of std_logic
• Two new data types: unsigned, signed
• The array interpreted as an unsigned or signed binary number
• E.g.,
• signal x, y: signed(15 downto 0);
• Need invoke package to use the data type
E.g.,
LIBRARY ieee; SIGNAL a, b, c, d: UNSIGNED (7 DOWNTO 0);
USE ieee.std_logic_1164.all; . . .
USE ieee.numeric_std.all; a <= b + c;
d <= b + 1;
e <= (5 + a + b) – c;

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 25

IEEE numeric-std: Unsigned or Signed Number…
• Signed and unsigned, are defined in the package.
• Both data types are an array of elements with the std-logic data type
• Unsigned data type:
• the array is interpreted as an unsigned binary number, with the leftmost element as
the MSB of the binary number.
• Signed data type:
• the array is interpreted as a signed binary number in 2’s-complement format.
• The leftmost element is the MSB of the binary number, which represents the sign of
the number
• Std_logic_vector, unsigned and signed data types are all defined as an array of
elements with the std-logic data type
• Since VHDL is a strongly typed language, they are considered as three independent
data types.
• Example, consider a 4-bit binary representation “1100”. Can be interpreted as:
• 12  unsigned
• – 4  signed
• ‘1’, ‘1’, ‘0’, ‘0’  four independent bits ( e.g. four status signals)

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 26

Overloaded operators in IEEE numeric_std package

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 27

mod vs. rem
 mod has sign of divisor, thus n in a mod n
 rem has sign of dividend, thus a in a rem n

9 mod 5 =4 because 9 = 5*1 + 4 and

5>0&4>0

9 rem 5 =4 because 9 = 5*1 + 4 and

9>0&4>0

9 mod (-5) = -1 because 9 = (-5)*(-2) + (-1) and -5 <

0 & -1 < 0

9 rem (-5) = 4 because 9 = (-5)*(-1) + 4 and 9>0

&4>0

(-9) mod 5 = 1 because -9 = 5*(-2) + 1 and 5>0

&1>0

(-9) rem 5 = -4 because -9 = 5*(-1) + (-4) and

Prof. Christopher-9 < 0Dept
U. Ngene & -4 < 0 Engineering, Unimaid, Email: ngene@unimaid.edu.ng
of Computer 28
New functions in IEEE numeric_std package

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 29

 Type conversion

• Type conversion between

data types:
• type conversion function
• Type casting (for “closely
related” data types)

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 30

 Type conversion…
E.g.
-- Wrong
library ieee; s3 <= u3; -- type mismatch
use ieee.std_logic_1164.all; s4 <= 5; -- type mismatch
use ieee.numeric_std.all;
... -- Fix
signal s1, s2, s3, s3 <= std_logic_vector(u3); -- type casting
s4, s5, s6: std_logic_vector(3 downto 0); s4 <= std_logic_vector(to_unsigned(5,4));
signal u1, u2, u3, u4,
--Wrong
u6, u7: unsigned(3 downto 0); s5 <= s2 + s1; + undefined over std_logic_vector
signal sg: signed(3 downto 0); s6 <= s2 + 1; + undefined

--Wrong -- Fix
u7 <= sg + u1; -- + undefined over the types s5 <= std_logic_vector(unsigned(s2) +
unsigned(s1));
--Fix s6 <= std_logic_vector(unsigned(s2) + 1);
u7 <= unsigned(sg) + u1; -- ok, but be careful

Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 31

Guidelines for general VHDL
• Use the STD-LOGIC-VECTOR and STD-LOGIC data types
instead of the bit-vector or bit data types.

• Use the NUMERIC-STD package and the UNSIGNED and

SIGNED data types for synthesising arithmetic operations.

• Use only the descending range (i.e., DOWNTO) in the

array specification of the unsigned, signed and std-logic-
vector data types.

• Use parentheses to clarify the intended order of

evaluation.
Prof. Christopher U. Ngene Dept of Computer Engineering, Unimaid, Email: ngene@unimaid.edu.ng 32